1. A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control
- Author
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Ho-kyoung Lee, Jin-seok Kwak, Y.S. Park, Seok-Won Hwang, Woojin Lee, Yu-Rim Lee, Seok-Jung Kim, Min-Sang Park, Soo-In Cho, Seong-Jin Jang, Sang-Jun Hwang, Sang-Bo Lee, Jong-Soo Lee, Young-Hyun Jun, Seong-Ho Cho, Hyoung-Jo Heo, Young-Uk Jang, Young-Cheol Cho, and Won-Hwa Shin
- Subjects
Random access memory ,Dynamic random-access memory ,Hardware_MEMORYSTRUCTURES ,business.industry ,Computer science ,Integrated circuit ,CAS latency ,law.invention ,law ,Low-power electronics ,Embedded system ,Electrical and Electronic Engineering ,business ,Double data rate ,Computer hardware ,Dram ,System bus - Abstract
An 8 M /spl times/ 32 GDDR (graphic DDR) SDRAM operating up to 800-MHz clock (CLK) frequency is described. The GDDR SDRAM demands an effective control of CAS latency due to the large and wide number of CAS latencies at the CLK frequency. A wave-pipelined CAS latency control circuit is proposed to provide stable operation for the large and wide number of CAS latencies. The increase of CAS latency also causes a degradation of data bus efficiency at high-speed operation due to the large gap between input data (DINs) and output data (DOUTs) at the operation of write followed by read. A gapless write to read scheme improves the data bus efficiency by separating write data-path from read data-path for different banks accesses. Partial array activation commands can reduce the peak current, preventing the reduction of the data retention time of DRAM cells at high-speed operation. The GDDR SDRAM operates successfully at the CLK frequency of 800 MHz at 2.1 V and 700 MHz at 1.8 V, respectively. The power consumption is measured to be /spl sim/2 W at 1.9 V.
- Published
- 2005