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A 1.6Gb/s/pin double-data-rate SDRAM with wave-pipelined CAS latency control.
- Source :
- 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519); 2004, p210-210, 1p
- Publication Year :
- 2004
Details
- Language :
- English
- ISBNs :
- 9780780382671
- Database :
- Complementary Index
- Journal :
- 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)
- Publication Type :
- Conference
- Accession number :
- 80779492
- Full Text :
- https://doi.org/10.1109/ISSCC.2004.1332668