Search

As the speed of DRAM increases and the applications spread, DLLs for DRAM require low-jitter characteristics as well as wide operating range in frequency and voltage domains. Even though digital DLLs have improved jitter control schemes [1,2,4], it is difficult to reject the jitter of the external clock in real applications. Whether a PLL or DLL is used, it should have negative delay for phase compensation in DRAM [3]. We design PDLL that has a PLL and a DLL with different roles. The DLL, which is used for phase compensation, is digital with low power consumption. The PLL, which is used for jitter reduction, is a charge-pump type [5] with dual K VCO and self-mode-shifting scheme, using an unregulated power supply for flexibility in operating range. Powering the PLL with an unregulated power supply is made possible by the power-noise-management technique of V PP control and by using a pseudo-rank architecture to suppress V DD noise due to low VPP pumping efficiency.

We design a DLL that has a slew-rate controlled duty-cycle-correction (DCC) with a fully digital controlled duty-cycle-error detector and has the update gear circuit to shift update mode for low power consumption. The DLL is composed of a dual loop and two types of digital DCC, at the input and output, which have a higher DCC capability when combined. We also design a clock receiver that generates a robust clock from a poor clock source.

A new low power, low cost and high performance register-controlled digital delay locked loop with wide locking range is presented. The DLL has dual loops with single replica block, duty cycle correction enhance controller (DCCEC), smart power down controller (SPDC) for reducing the standby current during power down, and locking range doubler for wide locking range. The digital DLL used for 3 Gbps 512 Mb GDDR3 SDRAM is fabricated using an 80 nm DRAM Process. Experimental results show less than plusmn1% duty correction from external duty error of plusmn5%, less than 400 cycle locking time, 1.5 GHz operation frequency at 1.9 V, and a wide locking range from 50 MHz to 1.5 GHz.