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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology
- Source :
- ISSCC
- Publication Year :
- 2008
- Publisher :
- IEEE, 2008.
-
Abstract
- We design a DLL that has a slew-rate controlled duty-cycle-correction (DCC) with a fully digital controlled duty-cycle-error detector and has the update gear circuit to shift update mode for low power consumption. The DLL is composed of a dual loop and two types of digital DCC, at the input and output, which have a higher DCC capability when combined. We also design a clock receiver that generates a robust clock from a poor clock source.
Details
- Database :
- OpenAIRE
- Journal :
- 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
- Accession number :
- edsair.doi...........4b6e0d0fb4f9670bb5ee6c1eea2be2c2