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In this letter, we report the influence of p-GaN body doping concentration on the ON-state performance of vertical GaN trench MOSFETs. Decreasing the p-GaN body doping concentration leads to an enhanced maximum drain current ( ${I} _{D,\max}$ ), reduced specific ON-resistance ( ${R} _{ \mathrm{\scriptscriptstyle ON},\mathrm{sp}}$ ), but also a decreased threshold voltage ( ${V} _{th}$ ), suggesting that the p-GaN doping plays an important role in balancing the ${V} _{th}$ , ${R} _{ \mathrm{\scriptscriptstyle ON},\mathrm{sp}}$ and ${I} _{D,\max}$ in vertical GaN trench MOSFETs. Resulting from the tuning of Mg concentration in the p-GaN, we demonstrate high ON-performance including a high ${I} _{D,\max}$ of 2.8 kA/cm2, a low ${R} _{ \mathrm{\scriptscriptstyle ON},\mathrm{sp}}$ of 0.87 $\text{m}\Omega \cdot $ cm2, a large ${V} _{th}$ of 4.8 V in a quasi-vertical GaN trench MOSFET on sapphire with a 2.5- $\mu \text{m}$ -thick drift layer, while maintaining a breakdown voltage of 273 V.

In this article, we demonstrate normally-OFF p-GaN gate high electron mobility transistors (HEMTs) on Si with an ultrahigh breakdown voltage ( ${V}_{BR}$ ) and excellent saturation drain current. Benefiting from the optimized material growth of high-resistivity buffer, effective Al2O3 surface passivation with suppressed OFF-state leakage current, and proper management of the electric field on the p-GaN gate edge, the device with a gate–drain distance of $18.5~\mu \text{m}$ exhibits a ${V}_{BR}$ of 1344 V at ${I}_{D}$ of $1~\mu \text{A}$ /mm with grounded substrates, the highest among all the reported normally-OFF GaN-on-Si transistors. Well-restored high-density 2-D electron gas and efficient gate modulation enable the device with a high ${I}_{DS,max}$ of 450 mA/mm and a low specific ON-resistance of 3.92 $\text{m}\Omega \cdot $ cm2. Moreover, a large threshold voltage of 1.6 V (at ${I}_{D}$ of $10~\mu \text{A}$ /mm) and a steep subthreshold slope of 66 mV/dec have been achieved, with negligible threshold voltage shift upon long-term forward gate stress at 150 °C. These results illustrate the great potential of p-GaN gate HEMTs on Si for beyond 600-V applications.

This letter reports on the suppression of reverse leakage current ( ${I} _{r}$ ) in $\beta $ -Ga2O3 Schottky barrier diodes (SBDs) through Schottky barrier modification by a low power CF4-plasma treatment prior to Schottky metal deposition. Revealed by an x-ray photoelectron spectroscopy (XPS) analysis, the fluorine-plasma treatment brought an incorporation of fluorine ions and depletion of silicon donors in the near surface region of the $\beta $ -Ga2O3, and thus raised its surface potential by around 0.14 eV. Furthermore, insulating GaF x was likely created at the Schottky interface. Attributed to the fluorine-plasma- modified Schottky barrier, a reduced ${I} _{\mathbf {r}}$ by around four orders of magnitude and enhanced blocking voltage ( ${V} _{{block}}$ ) from 150 V to 470 V at ${I} _{r} = 100\mu $ A/cm2 have been achieved without degrading the forward characteristics. Different from the untreated device whose ${I} _{r}$ was purely governed by the thermionic field emission (TFE), the fluorine-plasma-treated SBD showed a greatly suppressed TFE-current until a space-charge limited current (SCLC) started to dominate at around −500 V.

High performance NiO/ $\beta $ -Ga2O3 heterojunction pn diodes were realized by applying a sputtered p-type NiO film onto a lightly doped n-type $\beta $ -Ga2O3 epitaxial layer. Taking advantage of the high barrier height against carriers within the pn heterojunction, the demonstrated device exhibited a high breakdown voltage ( ${V}_{B}{)}$ of 1059 V without optimized electric field management techniques, and before breakdown the reverse leakage current density remained below $1~\mu \text{A}$ /cm2. Simultaneously, a relatively low specific on-resistance ( $R_{\text {on, sp}}{)}$ of 3.5 $\text{m}\Omega \cdot \text {cm}^{{2}}$ was achieved. The built-in potential of the heterojunction that determined by a capacitance-voltage ( ${C}$ - ${V}$ ) measurement was around 2.4 eV. As discussed in terms of the energy band diagram of a type-II heterojunction, the conduction band and valence band offsets at the NiO/ $\beta $ -Ga2O3 hetero-interface were estimated to be 1.2 and 2.3 eV, respectively.

This work reports GaN quasi-vertical trench MOSFETs grown on 6-inch Si substrates. The device with single-trench design shows a specific ON-resistance of 0.84 mΩ·cm2, a maximum drain current density of 5.0 kA cm−2, and a breakdown voltage of 320 V, after fine-tuning of the channel doping and employment of a thick bottom dielectric process. The large-area (∼0.54 mm2) GaN-on-Si trench MOSFET with multiple-finger design shows an ON-current of 1.1 A, an ON-resistance of 4.0 Ω and a breakdown voltage of 205 V.

GaN offers an excellent potential for fabricating X-ray detectors, taking advantage of its superior material properties and well-developed manufacturing technologies. In this letter, we demonstrated a self-powered fast-response X-ray detection using GaN-based vertical p-n diodes grown on a bulk GaN substrate. Attributed to the high crystalline quality achieved by homoepitaxy, the fabricated photodiodes exhibited an excellent rectification behavior, and therefore, a strong photovoltaic response to X-ray illumination when biased at 0 V. The transient X-ray detection analysis revealed that the self-powered detectors have a relatively short response time ( $\cdot $ Gy $^{ {-{1}}}\cdot $ cm−2.

In this letter, we report high-performance p-GaN HEMTs on Si with robust gate operation. For the first time, the preserved OFF-state drain blocking capability has been demonstrated in p-GaN HEMTs after forward gate breakdown. Benefitting from the reduced metal/p-GaN contact region, the gate breakdown was limited to take place only at the metal/p-GaN junction, with the p-GaN/AlGaN/GaN junction intact. The device shows state-of-the-art characteristics with a large threshold voltage of 1.75 V at ${I}_{\text {D}}$ of $100~\mu \text{A}$ /mm (2.3 V by linear extrapolation), a high maximum drain current of 610 mA/mm at ${V}_{\text {GS}}$ of 8 V, a low specific ON-resistance of 1.8 $\text{m}\Omega \cdot \text {cm}^{{2}}$ , and a high breakdown voltage of 1100 V defined at ${I} _{\text {D}}$ of $1~\mu \text{A}$ /mm with grounded substrate.

Vertical GaN trench MOSFETs have shown enormous potential for efficient power switching applications. Low ON-resistance ( RON) to minimize power loss, high output current ( ION) to maximize driving capability, and large threshold voltage ( Vth) to avoid false turn-on are highly desirable. This work reports vertical GaN trench MOSFETs with step-graded channel doping. Conventional devices with uniform channel doping were involved for comparison. The experimental results show that step-graded channel doping can achieve an improved trade-off between ION, RON, and Vth than uniform channel doping.

We report on the power performance of GaN-on-Si metal–oxide–semiconductor high electron mobility transistors (MOSHEMTs) with a high- ${k}$ ZrO2 gate dielectric formed by atomic layer deposition. As a result of the high-quality ZrO2 and ZrO2/AlGaN interface, the MOSHEMTs demonstrate an excellent ON/OFF current ratio of $5 \times 10^{10}$ , a steep subthreshold slope of 66 mV/dec, a small hysteresis of ~0.05 V, and a high breakdown voltage of 1084 V at $1~\mu \text{A}$ /mm. Effective suppression of current collapse with a dynamic-to-static ON-resistance ratio of 1.78 at a drain bias of 600 V is also achieved in the device. Benefiting from the highly uniform gate stack, large-area devices with a gate width of 20 mm were also demonstrated using the ZrO2 gate dielectric, exhibiting a maximum output current of 7.4 A, a low ON-resistance of $0.66~\Omega $ , and a high breakdown voltage of 650 V at an OFF-state drain current of $1~\mu \text{A}$ /mm.

Enhancement-mode GaN MOS-HEMTs with a uniform threshold voltage ( ${V}_{\text {th}}\sim \text {2.2 }\pm \text {0.25}$ V at ${I}_{D}= \text {1}\,\,\mu \text{A}$ /mm) have been achieved by a recess-free barrier engineering technique in conjunction with a high- ${k}$ gate dielectric. The design includes an ultrathin (~6 nm) Al0.2Ga0.8N barrier preserving the two dimensional electron gas (2DEG) mobility underneath the gate and a selective area barrier regrowth to restore the 2DEG at the access regions. A high- ${k}$ ZrO2 gate dielectric was employed to enhance the gate control over the channel. The common issue of recess-induced damage was mitigated. The high-quality gate stack results not only in a highly uniform and large ${V}_{\text {th}}$ , but also small hysteresis, minimal gate lag, low on-resistance, and high output current in the E-MOS-HEMTs.

An auto-zero-voltage-switching (ZVS) quasi-resonant LED driver with gallium nitride (GaN) FETs for general lighting applications is presented. The proposed LED driver switches at high frequency to minimize the inductors to microhenry range. ZVS can be automatically achieved with the proposed controller to eliminate switching loss. The GaN FETs enable high-frequency operation and improve the power efficiency. A fully integrated LED shunt protector is proposed to bypass the failed LEDs in series-connected LED strings. The overall lifetime of the LED strings can be improved, and the maintenance cost can be reduced. The characteristics of the ZVS quasi-resonant LED driver with small inductors and the conditions for ZVS are also discussed in detail. The LED driver is fabricated with a 0.35- $\mu \text{m}$ 120-V high-voltage process. It can provide up to 25-W power to the LED with $2 \times 3.3\,\,\mu \text{H}$ inductors and achieves 91.4% peak efficiency and a 0.973 peak power factor from 60-Hz 100- to 120- $\text{V}_{\mathrm {ac}}$ input.

This letter reports the monolithic integration of GaN-based driving vertical metal–oxide–semiconductor field-effect transistor (VMOSFET) on light-emitting diode (LED) with high output current density and bright-ness. By selectively regrowing a simple p- and n-GaN bilayer on top of an LED wafer, the VMOSFET was realized with an n/p/n structure and intrinsically connected with the LED through the bottom conductive n-GaN layer. During the fabrication, a tetramethylammonium hydride wet etch technique was employed to smoothen the sidewall channel surface of the VMOSFET and to enhance its channel electron mobility, consequently achieving a high output current density exceeding 1.4 kA/cm2. The integrated VMOSFET-LED exhibited a high light output power of 8.5 mW or 9.4 W/cm2 with a modulated injection current of 10 mA through the VMOSFET, showing a great potential of such integration scheme for a variety of smart-lighting applications.

Interface trapping is one of the most notorious effects that limit device performance in GaN-based MIS high electron mobility transistors (MISHEMTs). In this paper, we present a comprehensive study on interface traps in AlGaN/GaN MISHEMTs using low pressure chemical vapor deposition SiNx as gate dielectric. We combined the trapping analysis in MIS diodes and actual MISHEMTs to estimate the interface trap state densities ( $\text{D}_{\mathrm {it}})$ and their distributions in the device, and to investigate their influence on device electrical properties. Two types of interface traps with different emission time constants, designated as “slow” and “fast” traps, were identified and characterized by means of pulse-mode current-voltage measurements and a frequency dependent conductance method. It was found that “fast” traps located in the device access region could be effectively restrained by passivation using plasma enhanced chemical vapor deposition SiNx. However, “slow” traps, no matter whether located beneath the metal gate or in the access region, were less influenced by passivation. Due to the strong interference of traps in the access region, $\text{D}_{\mathrm {it}}$ extraction using the conventional conductance method was not accurate for the lateral GaN-based MIS diodes. A modified small-signal equivalent circuit that includes the impedance of traps in the access region is proposed. Proper passivation for the device access region is essential when using the conductance method for GaN-based MIS devices.

In this paper, we present a systematic investigation of metal–organic chemical vapor deposition-grown in situ SiN as the gate dielectric and surface passivation for AlGaN/GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs). The dielectric constant and breakdown field of the in situ SiN were extracted from devices with varied gate dielectric thicknesses. Using frequency-dependent capacitance–voltage and parallel conductance methods, we obtained a low trap density of $\sim 3\times 10^{12}$ cm $^{-2}$ eV $^{-1}$ at the SiN/AlGaN interface. The MISHEMTs with a source–drain distance of $3~\mu \text{m}$ show a maximum drain current of 1560 mA/mm and a high on/off current ratio of $10^{9}$ . The device threshold voltage ( ${V}_\textsf {th}$ ) stability was assessed by means of both negative and positive gate stress measurements, as well as temperature-dependent $ {I}_\textsf {D}$ – ${V}_\textsf{G}$ measurements. We observed a minimal $ {V}_\textsf{th}$ shift of ~0.4 V under both 3000 s gate stress of ${V}_\textsf {GS}= 4$ V and up to 200 °C thermal stimulation. Furthermore, combining the in situ SiN with plasma-enhanced chemical vapor deposition SiN, we developed a bilayer passivation scheme for effective suppression of current collapse. Employing the high-quality in situ SiN, we have demonstrated large-area GaN MISHEMTs on Si with a gate width of 20 mm, showing a low off-state leakage of $2~\mu \text{A}$ /mm at 600 V and a low dynamic/static ON-resistance ratio. The device results show great advantages of employing in situ SiN in D-mode GaN MISHEMTs for high-efficiency power switching applications.

In this letter, a novel monolithically integrated Si-GaN cascoded FET is designed and experimentally demonstrated for high-voltage power switching applications. The device is formed by monolithically connecting a low-voltage Si MOSFET and a high-voltage normally-on GaN MIS-HEMT on the same substrate in the cascode configuration. The interconnection distance is $50~\mu \text{m}$ which is only 2.5% of that of the conventional two-chip co-package approach (~2 mm). The fabricated cascoded FET features normally-off functionalities with a threshold voltage of 3.2 V, a drive current of 1850 A/cm2 (630 mA/mm) at the gate bias of 15 V, a gate swing of 20 V, a specific on-resistance of $3.3\;\text {m}\Omega \cdot \text {cm}^{2}$ and a breakdown voltage of 696 V.

This paper reports a p-GaN/AlGaN/GaN heterostructure photodetector (PD) with high responsivity and high photo-to-dark current ratio $(\mathrm{I}_{\mathrm{ph}}/\mathrm{I}_{\mathrm{dark}})$ . Due to the inherent depletion of the 2-D electron gas in the heterostructure by the p-type GaN, the dark current of the PD is significantly suppressed without compromising the advantages of high photocurrent and responsivity in AlGaN/GaN heterostructure PDs. As a result, both a large responsivity of $2\times 10^{4}\ \mathrm{A}/\mathrm{W}$ and a high $\mathrm{I}_{\mathrm{p}\mathrm{h}}/\mathrm{I}_{\mathrm{dark}}$ of 107 at a bias of 5 V were achieved in our device under UV light with a wavelength of 365 nm and intensity of $5\ \mu \mathrm{W}/\mathrm{mm}^{2}$ . Moreover, a large UV to visible rejection ratio of around 3000 was also observed in the device. The superior device performance in our work compared to other reported results suggests the great potential using the p-GaN/AlGaN/GaN heterostructure based PDs for high-sensitivity UV detection.

In this study, we developed $\beta$ -Ga 2 O 3 -based vertical Schottky barrier diodes (SBDs) and investigated their switching performance. The devices were fabricated by epitaxy of an $\mathrm{n}^{-}-\beta$ -Ga 2 O 3 drift layer on an n-type (001) $\beta$ -Ga 2 O 3 substrate and using Pt as the Schottky metal. The SBDs showed an excellent Schottky contact with a low ideality factor of ~1.02 and a high on/off current ratio $(\mathrm{I}_{\mathrm{ON}}/\mathrm{I}_{\mathrm{OFF}})$ of over 6 orders of magnitude at −300 V. The reverse recovery characterization of the $\beta$ -Ga 2 O 3 SBD was performed and compared with a commercial Si fast-recovery diode (FRD). When switching from an on-state current of 350 mA to a reverse-blocking voltage of −100 V, the vertical $\beta$ -Ga 2 O 3 SBD exhibits fast reverse recovery with a reverse recovery time $(\mathrm{t}_{\mathrm{rr}})$ of ~14.1 ns and reverse recovery charge $(\mathrm{Q}_{\mathrm{rr}})$ of ~ 0.34 nC, outperforming the Si FRD of similar ratings. In addition, the Si FRD showed significantly increased $\mathrm{t}_{\mathrm{rr}}$ and $\mathrm{Q}_{\mathrm{rr}}$ when the on-state current was set higher, while the $\beta$ -Ga 2 O 3 SBDs exhibited similar behavior when switched-off from various level of on-state current. The results demonstrate the great potential of $\beta$ -Ga 2 O 3 SBDs for high-speed switching applications.

In this letter, we report the first demonstration of monolithically integrated ultraviolet (UV) light emitting diodes (LEDs) and visible-blind UV photodetectors (PDs) employing the same p-GaN/AlGaN/GaN epi-structures grown on Si. Due to the radiative recombination of holes from the p-GaN layer with electrons from the 2-D electron gas (2DEG) accumulating at the AlGaN/GaN heterointerface, the forward biased LED with p-GaN/AlGaN/GaN junction exhibits uniform light emission at 360 nm. Facilitated by the high-mobility 2DEG channel governed by a p-GaN optical gate, the visible-blind phototransistor-type PDs show a low dark current of ∼10−7 mA/mm and a high responsivity of 3.5×105 A/W. Consequently, high-sensitivity photo response with a large photo-to-dark current ratio of over 106 and a response time less than 0.5 s is achieved in the PD under the UV illumination from the on-chip adjacent LED. The demonstrated simple integration scheme of high-performance UV PDs and LEDs shows great potential for various applications such as compact opto-isolators.

We report three dimensional (3D) disk-shaped GaAs crystals on V-groove patterned (001) Si substrates by metalorganic chemical vapor deposition. Planar GaAs nanowires with triangular cross-sections were grown inside Si V-grooves by nano-scale selective heteroepitaxy. These nanowires were then partially confined in micro-sized SiO2 cavities and coalesced into uniform arrays of 3D crystals. Scanning electron microscope and atomic force microscopy inspection showed the absence of antiphase-domains and smooth top surface morphology. Superior structural and optical properties over GaAs thin films on planar Si were also demonstrated. More remarkably, by growing the 3D crystals on V-grooved Si, we were able to overcome the residual tensile stress induced by the thermal mismatch between GaAs and Si. Strain-free GaAs was uncovered in the crystals with a dimension of 3×3 µm2.

For the development of a metal-interconnection-free integration scheme for monolithic integration of InGaN/GaN light-emitting diodes (LEDs) and AlGaN/GaN high-electron-mobility transistors (HEMTs), a common buffer to achieve high brightness, low leakage current, and high breakdown in the integrated HEMT–LED device is essential. Different buffer structures have been investigated, and their impacts upon both the LED and HEMT parts of the HEMT–LED device have been analyzed. Results indicated that a GaN/AlN buffer structure is the most ideal to serve as a common buffer platform, offering both the excellent crystalline quality and superior buffer resistivity required by the HEMT–LED device. Growth of the AlN layer was particularly crucial for engineering the dislocation density, surface morphology, as well as resistivity of the buffer layer. Using the optimized GaN/AlN buffer structure, the LED part of the HEMT–LED device was improved, showing greatly enhanced light output power and suppressed reverse leakage current, while the breakdown characteristics of the HEMT part were also improved.

We report high performance ultraviolet (UV) photodetectors (PDs) based on p-GaN-gated AlGaN/GaN heterostructures grown on silicon substrates. Benefitting from the high electrical gain resulting from the transistor-like operation of the device, a photocurrent as high as 4.8 mA/mm was achieved with UV illumination. Due to the effective depletion of the two-dimensional electron gas at the AlGaN/GaN heterointerface via a p-GaN optical gate, the dark current was suppressed to below 3 × 10−8 mA/mm. A high photo-to-dark current ratio over 108 and a high responsivity of 2 × 104 A/W were demonstrated in the device. Moreover, with a cutoff wavelength of 395 nm, the PDs exhibited an ultrahigh UV-to-visible rejection ratio of over 107. Limited by a persistent photoconductivity effect, the rise time and fall time of the device frequency response were measured to be 12.2 ms and 8.9 ms, respectively. The results suggest the potential of the proposed PDs for high-sensitivity UV detection.

In this paper, fabrication process of the fully integrated Si-GaN cascoded field effect transistor is presented first. Device performance of the individual Si MOSFET and AlGaN/GaN MIS-HEMT, which are fabricated along with the Si-GaN cascoded FET, are then characterized. Finally, the device performance of the fully integrated cascoded FET is characterized in detail, including the transconductance compression at high V GS and high V DS , the reverse conduction, the power figure-of-merit (FOM), and the high-temperature characteristics. It is shown that the Si-GaN monolithic cascoded FET is a promising candidate for high performance power switching applications.

Impact of post metallization annealing (PMA) on the off-state drain leakage (Ioff) for Al2O3/GaN/AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) on Si has been investigated. After implementation of PMA at 500 °C for 10 min in N2 ambient, the Ioff can be reduced by three orders of magnitude compared to that without PMA. In consequence, a high on/off current ratio of 108 and a steep subthreshold slope of 71 mV/dec are achieved for the MOSHEMTs. The reduction of Ioff results from the suppression of source-drain surface leakage through the interface between Al2O3 and GaN. The decrease of accumulation capacitance of the MOS capacitors (MOSCAPs) after 500 °C PMA suggests an oxidation process at the GaN surface during the high temperature annealing, which was confirmed by the increase of oxide layer thickness measured by transmission electron microscopy (TEM), and also the increase of GaO/GaN bond ratio at the Al2O3/GaN interface revealed by X-ray photoelectron spectroscopy (XPS). These results suggest that the significant reduction of Ioff after 500 °C PMA can be attributed to partial surface oxidation of the GaN cap, which suppresses the conduction path at the Al2O3/GaN interface.

This paper reports on the fabrication and characterization of gate-last self-aligned in situ SiN x /AlN/GaN MISHEMTs. The devices featured in situ grown SiN x by metal–organic chemical vapor deposition as a gate dielectric and for surface passivation. Selective source/drain regrowth was incorporated to reduce contact resistance. SiN x sidewall spacers and low- $\kappa $ benzocyclobutene polymer ( $\kappa =2.65$ ) supporting layers were employed under the gate head to minimize the parasitic capacitance for high-frequency operation. The device with a gate length ( $L_{G})$ of $0.23~\mu \text{m}$ exhibited a maximum drain current density ( $I_{\rm DS})$ exceeding 1600 mA/mm with a high ON/OFF ratio ( $I_{\mathrm{{\scriptscriptstyle ON}}}/I_{\mathrm{{\scriptscriptstyle OFF}}})$ of over $10^{7}$ . The current gain cutoff frequency ( $f_{T})$ and maximum oscillation frequency ( $f_{\max })$ were 55 and 86 GHz, respectively. In addition, the effect of temperature, from room temperature up to 550 K, on the dc and RF performances of the gate-last self-aligned MISHEMTs was studied.

We report the MOVPE growth of high-performance AlN/GaN MISHEMTs using regrown n-type GaN (n-GaN) as source/drain (S/D) and in situ SiNx as gate dielectric. The n-GaN S/D and in situ SiNx were investigated for minimizing on-resistance and suppressing gate leakage current, respectively. The results showed that a two-step Si doping profile for the n-GaN greatly reduced the access resistance, and small gate leakage as well as low trap state density were achieved with the in situ SiNx gate dielectric. The fabricated 0.33 μm-gated MISHEMT exhibited a maximum drain current density of 1550 mA/mm and an on/off current ratio over 107.

In situ SiNx grown by metal-organic chemical vapor deposition (MOCVD) was employed as the gate dielectric for ultra-thin-barrier AlN/GaN metal-insulator-semiconductor high electron mobility transistors (MISHEMTs) on Si substrates. Despite the ultra-thin barrier of 1.5 nm, low reverse leakage current of below 10−7 A cm−2 was obtained with a 7 nm in situ SiNx gate dielectric. The good surface passivation effects of in situ SiNx were also demonstrated by the enhanced source/drain (S/D) current density and the reduced drain current degradation. Furthermore, interface trapping effects in the in situ SiNx/AlN/GaN heterostructures were investigated by double-mode capacitance–voltage (C–V) measurements and frequency dependent conductance analysis. A trap states density of 1.9–3.4 × 1012 cm−2 eV−1 with a time constant of 0.8–17 µs were deduced.

Herein, vertical Schottky barrier diodes (SBDs) based on a bulk beta-Ga2O3 substrate are developed. The devices feature an ion-implanted planar edge termination (ET) structure, which can effectively smoothen the electric field peak and reduce the electric field crowding at the Schottky junction edge. Greatly enhanced reverse blocking characteristics including approximate to 10(3)x lower reverse leakage current and 1.5x higher breakdown voltage (V-B) are achieved, whereas good forward conduction such as a reasonably high on-state current density and near-unity ideality factor is maintained. In addition, the switching performance of the fabricated vertical beta-Ga2O3 SBDs is investigated using a double-pulse test circuit. When switching from an on-state current of 350 mA to a reverse-blocking voltage of -100 V, the vertical beta-Ga2O3 SBDs exhibit fast reverse recovery with a reverse recovery time (t(rr)) of approximate to 14.1 ns and reverse recovery charge (Q(rr)) of approximate to 0.34 nC, outperforming the Si fast recovery diode (FRD) of similar ratings. The results indicate a great promise of vertical beta-Ga2O3 SBDs for high-voltage fast switching applications.

This work reports the fabrication of AlGaN/GaN HEMTs with regrown ohmic contacts using either a passivation-last or a passivation-first process, where the order of surface passivation and gate metallization processes is different. An improved performance is demonstrated using the passivation-first process, achieving a maximum current/power gain cutoff frequency (f T /f max ) around 60/127 GHz with an 80-nm gate length. The ohmic contacts were regrown with highly doped n-GaN, resulting in a contact resistance of ∼0.2 Ω·mm. The RF performance can be further enhanced by reducing the extrinsic gate capacitance and short channel effects.

We report enhanced gate stack stability in GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs) by using a bilayer SiNx as the gate dielectric. To obtain the bilayer gate dielectric scheme, a thin Si-rich SiNx interlayer was deposited before a high-resistivity SiNx layer by low pressure chemical vapor deposition. The Si-rich SiNx can effectively suppress the trapping phenomenon at the interface of the dielectric/AlGaN barrier. The upper high-resistivity SiNx layer can greatly block the gate leakage current to enable a large gate swing. Compared with the MISHEMTs using a single Si-rich or high-resistivity SiNx layer, the MISHEMTs with a bilayer gate dielectric take the advantages of both, realizing a gate stack with a stable threshold voltage and low leakage current. These results thus present great potential for developing high-performance GaN MISHEMTs using the bilayer SiNx gate dielectric scheme for highly efficient power applications. Published by AIP Publishing.

We report for the first time on-chip integration of III-nitride voltage-controlled light emitters with visible and ultraviolet (UV) photodiodes (PDs). InGaN/GaN and AlGaN/GaN heterostructures were grown in specific regions by selective-area epitaxy, allowing monolithic integration of versatile devices including visible light emitting diodes (LEDs), visible-light PDs, AlGaN/GaN high electron mobility transistors (HEMTs), and UV-light Schottky barrier (SB) PDs. A serial connection between the LED and HEMT through the epitaxial layers enables a three-terminal voltage-controlled light emitter (HEMT-LED), efficiently converting voltage-controlled signals into visible-light signals that can be coupled into an adjacent visible-light PD generating electrical signals. While the integrated blue HEMT-LED and PD transmits signals carried by visible light, the visible-blind SB-PD on a chip receives external UV light control signals with negligible interference from the on-chip visible-light source. This integration scheme can be extended to open an avenue for developing a variety of applications, such as smart lighting, on-chip optical interconnect, optical wireless communication, and opto-isolators.

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec−1, and a field-effect electron mobility of 12.1 cm2 V−1 s−1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm−1 at V DS = 5 V. The gate leakage current is below 10−2 A cm−2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm−1 is obtained. Gate hysteresis and frequency-dependent capacitance–voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ~3 × 1012 cm−2 eV−1.

In this letter, monolithic integration of InGaN/GaN light emitting diodes (LEDs) with vertical metal-oxide-semiconductor field effect transistor (VMOSFET) drivers have been proposed and demonstrated. The VMOSFET was achieved by simply regrowing a p- and n-GaN bilayer on top of a standard LED structure. After fabrication, the VMOSFET is connected with the LED through the conductive n-GaN layer, with no need of extra metal interconnections. The junction-based VMOSFET is inherently an enhancement-mode (E-mode) device with a threshold voltage of 1.6 V. By controlling the gate bias of the VMOSFET, the light intensity emitted from the integrated VMOSFET-LED device could be well modulated, which shows great potential for various applications, including solid-state lighting, micro-displays, and visible light communications.

We report on the reduction of off-state leakage current in AlGaN/GaN high electron mobility transistors (HEMTs) by a two-step process combining pre-gate surface treatment and post-gate annealing (PGA), which suppressed the two leakage paths, namely, lateral surface leakage and vertical tunneling leakage, separately. The lateral surface leakage current, which was mainly induced by the high-density trap states generated during the device isolation etching process, was significantly reduced by a low power O2-plasma and HCl surface treatment process. The PGA process reduced the vertical tunneling leakage current by improving the Schottky contact quality of the transistor gate. Consequently, the device off-state leakage current was decreased by about 7 orders of magnitude and no degradation was introduced to the on-state performance, leading to a high on/off current ratio of 1010 and steep subthreshold slope (SS) of 62 mV/dec. The origin and leakage suppression mechanisms are also investigated and discussed in detail.

We report the use of SiNx grown in situ by metal-organic chemical vapor deposition as the gate dielectric for AlN/GaN metal-insulator-semiconductor (MIS) structures. Two kinds of trap states with different time constants were identified and characterized. In particular, the SiNx/AlN interface exhibits remarkably low trap state densities in the range of 1011–1012 cm−2eV−1. Transmission electron microscopy and X-ray photoelectron spectroscopy analyses revealed that the in situ SiNx layer can provide excellent passivation without causing chemical degradation to the AlN surface. These results imply the great potential of in situ SiNx as an effective gate dielectric for AlN/GaN MIS devices.

SiNx grown in situ by metalorganic chemical vapor deposition (MOCVD) has shown great potential as a high-quality gate dielectric and surface passivation for AlN/GaN heterostructure transistors. In this paper, we present a thorough study on how the growth conditions affect the film quality of SiNx and correlate the observed material properties with the electrical characteristics of the heterostructures. Lowering the growth pressure and SiH4/NH3 ratio can improve the SiNx/AlN interface roughness, leading to a reduced interfacial trap state density. The gate leakage current can be suppressed by increasing the resistivity of SiNx, which can be tailored with growth temperature and SiH4/NH3 ratio.

Structural and electronic properties of Zn-doped cubic boron nitride (cBN) were investigated via first principle calculation based on density functional theory. Our simulation suggests that Zn can substitute for both B (ZnB) and N (ZnN) atom; ZnB is energetically favorable, and ZnN can only be prepared under B-rich conditions. ZnB induced a shallow acceptor level; however, the large difference in electronegativity between Zn and N makes the acceptor level strongly localized, which reduces effective carrier density. In the case of ZnN, both deep acceptor levels within band gap and shallow acceptor levels at the top of valence band were induced, which produced more free carriers than ZnB. The calculated results account for experimental results of enhanced electric conductivity of Zn-doped cBN films prepared under B-rich conditions.

We report an investigation of in situ SiNx gate dielectric grown on AlN/GaN heterostructures by metal-organic chemical vapor deposition. It is revealed that the in situ SiNx is Si-rich, with a N/Si ratio of 1.21 and a relatively high effective dielectric constant of ∼8.3. The 7 nm in situ SiNx film exhibited a large resistivity of >1014 Ω · cm and a breakdown field of 5.7 MV/cm. Furthermore, interface trapping effects in the in situ SiNx/AlN/GaN heterostructures were investigated by frequency dependent conductance analysis.