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Silicon (Si)-based quantum-dot (QD) device by advanced CMOS process is one of important technologies for quantum computing application and currently, it needs a fast and accurate quantum characteristics simulation for designing and optimizing the devices. In this paper, for the first time, a fast hybrid simulation method is proposed by incorporating simplified quantum master equation model with the traditional TCAD tool. Additionally, a SPICE MODEL is incorporated for transient current correction to achieve results closer to real observations. The QD devices forming on advanced stacked Si nanowire (NW) and stacked Si nanosheet (NS) are constructed and simulated by this method, yielding Coulomb diamond plot and charge energies for different structures at 1 K. Notably, a Coulomb blockade region of approximately 82 mV and a first Coulomb step width approximately 1.6 times wider than the blockade region are observed, consistent with theoretical expectations and confirming the method’s efficacy. Simulation characteristics of advanced diamond-like channel devices are obtained within 1277 s, demonstrating over 85% matching with experimental data. Meanwhile, the influence of quantum characteristics varying with the transistor’s structure and process parameters is also analyzed, which in turn provide a guidance for the design and the optimization of the QD device by advanced Si CMOS process.

One-dimensionalcarbon nanotube field-effect transistors (CNFETs) have offered a solution for obtaining high transistor performance in a compatible low-temperature BEOL process, enabling monolithic 3D integration benefits for more functional circuits. Currently, CNT transistors need to further improve their performance with a more stable process and explore the most suitable circuit application scene. In this study, we successfully enhanced the performance of CNFETs through special Y2O3 film passivation and vacuum annealing processes. The on-state current of the optimized device was improved by $36.6\times $ compared to the device without these processes. Besides, the subthreshold swing (SS) was notably reduced from 259 mV/dec to 215 mV/dec and the threshold voltage was decreased from 2.02 V to 1.79 V due to the reduction of the interface state. Meanwhile, the devices’ optoelectronic characteristics were significantly improved and exhibited a $72\times $ increase in $\Delta $ Ids under identical illumination. With an improved annealing process, the $\Delta $ Ids were further increased to $231\times $ compared to the original device because of the reduction of defects within the device. Finally, the tentative Morse code communication applications all by the optimized CNFETs were obtained. These technologies and functional implementations provided a promising approach for future 3D functional communication systems with CNT technology.

In this article, a partially isolated dual work function (PIDWF) gate In-Ga-Zn-O (IGZO) thin-film transistor (TFT) is proposed to reduce the off-state current (Ioff) obviously, which also provides a feasible integration method for stacking IGZO TFT on Si-based devices. It is found that compared with the general back gate IGZO TFT structure, the Ioff of the proposed IGZO TFT reduces from $2.57\times 10{^{-}14 }$ A/ $\mu $ m to $7.57\times 10{^{-}16 }$ A/ $\mu $ m, achieving two orders of magnitude improvement. This breakthrough has the potential to increase the retention time of DRAM applications by nearly 100 times. Moreover, the pronounced novel structure has mitigated parasitic capacitance, thereby leading to a notable 47.7% reduction in write latency within dynamic-random-access-memory (DRAM) circuits. The relevant operation mechanism is carefully demonstrated and verified by the simulation of the electric field and potential barrier results by technical computer-aided design (TCAD). Furthermore, the impacts of the dual gate work function level, the length, and the type of isolation dielectric between dual work function gates are systematically investigated. The results show that the off-state leakage is further reduced by increasing the difference of the work function levels between in dual gates, the dielectric length (LD) and using the isolation layer with a lower dielectric constant. The PIDWF gate IGZO TFT exhibits scalability and is capable of achieving an 84.6% reduction in leakage current even with ultra-short channel lengths, which offers a promising application for future 3D DRAM applications with little extra cost.

Amorphous oxide semiconductor-thin film transistors (AOS-TFTs) have attracted considerable attention due to their impressive performance in various applications. However, there is a limited amount of study available on the reliability of AOS-TFTs. This work investigates the endurance and reliability mechanisms of Indium Gallium Zinc Oxide (IGZO) and Indium Tin Oxide (ITO) TFTs. The devices underwent a range of test conditions to evaluate their endurance properties. The study utilized Zero-Bias Endurance Tests (ZBET) to examine the fluctuating behaviors of threshold voltage, revealing valuable insights into the causes of electrical instability. The study highlights the crucial importance of electron depletion and restoration dynamics in affecting the reliability of TFTs. Additionally, the study found differences in the performance of IGZO-TFTs and ITO-TFTs, suggesting that the differing features of the materials have a significant impact on the endurance and reliability of TFTs.

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Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.

Silicon nanowire field effect (SiNW-FET) biosensors have been successfully used in the detection of nucleic acids, proteins and other molecules owing to their advantages of ultra-high sensitivity, high specificity, and label-free and immediate response. However, the presence of the Debye shielding effect in semiconductor devices severely reduces their detection sensitivity. In this paper, a three-dimensional stacked silicon nanosheet FET (3D-SiNS-FET) biosensor was studied for the high-sensitivity detection of nucleic acids. Based on the mainstream Gate-All-Around (GAA) fenestration process, a three-dimensional stacked structure with an 8 nm cavity spacing was designed and prepared, allowing modification of probe molecules within the stacked cavities. Furthermore, the advantage of the three-dimensional space can realize the upper and lower complementary detection, which can overcome the Debye shielding effect and realize high-sensitivity Point of Care Testing (POCT) at high ionic strength. The experimental results show that the minimum detection limit for 12-base DNA (4 nM) at 1 × PBS is less than 10 zM, and at a high concentration of 1 µM DNA, the sensitivity of the 3D-SiNS-FET is approximately 10 times higher than that of the planar devices. This indicates that our device provides distinct advantages for detection, showing promise for future biosensor applications in clinical settings.

Artificial synapses are key elements in building bioinspired, neuromorphic computing systems. Ferroelectric field‐effect transistors (FeFETs) with excellent controllability and complementary metal oxide semiconductor (CMOS) compatibility are favorable to achieving synaptic functions with low power consumption and high scalability. However, because of the only nonvolatile ferroelectric (Fe) characteristics in the FeFET, it is difficult to develop bioplausible short‐term synaptic elements for spatiotemporal information processing. By judiciously combining defects (DE) and Fe domains in gate stacks, a compact artificial synapse featuring spatiotemporal information processing on a single Fe–DE fin FET (FinFET) is proposed. The devices are designed to work in a separate DE mode to induce short‐term plasticity by spontaneous charge detrapping, and a hybrid Fe–DE mode to trigger long‐term plasticity through the coupling of defects and Fe domains. The capability of the compact synapse is demonstrated by differentiating 16 temporal inputs. Moreover, the highly controllable static electricity of advanced FinFETs leads to an ultralow power of 2 fJ spike−1. An all Fe–DE FinFET reservoir computing (RC) system is then constructed that achieves a recognition accuracy of 97.53% in digit classification. This work enables constructing RC systems with fully advanced CMOS‐compatible devices featuring highly energy‐efficient and low‐hardware systems.

Abstract In this work, extremely thin silicon-on-insulator field effective transistors (ETSOI FETs) are fabricated with an ultra-thin 3 nm ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer. Furthermore, the subthreshold characteristics of the devices with double gate modulation are investigated extensively. Contributing to the advantages of the back-gate voltage coupling effects, the minimum subthreshold swing (SS) value of a 40 nm ETSOI device could be adjusted from the initial 80.8–50 mV/dec, which shows ultra-steep SS characteristics. To illustrate this electrical character, a simple analytical model based on the transient Miller model is demonstrated. This work shows the feasibility of FE ETSOI FET for ultra-low-power applications with dynamic threshold adjustment.

With characteristic size scaling down to the nanoscale range, the confined geometry exacerbates the self-heating effect (SHE) in nanoscale devices. In this paper, the impact of ambient temperature (Tamb) on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks (Nstack) increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends. To compare the effect of different Tamb ranges, the temperature coefficients of current per stack and threshold voltage are analyzed. As the Nstack increases from 4 to 32, it is verified that the zero-temperature coefficient bias point (VZTC) decreases significantly in p-type nanoscale devices when Tamb is above room temperature. This can be explained by the enhanced thermal crosstalk. Then, the gate length-dependent electrothermal characteristics with different Nstacks are investigated at various Tambs. To explore the origin of drain current variation, the temperature-dependent backscattering model is utilized to explain the variation. At last, the simulation results verify the impact of Tamb on the SHE. The study provides an effective design guide for stacked nanosheet transistors when considering multiple stacks in circuit applications.

A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio ( $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ ) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.

Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of Si0.7Ge0.3. Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and storage density. Previous work investigated ICP selective etching of a three-cycle Si0.7Ge0.3/Si multilayer structure and the related etching effects. This study focuses on the dry etching of a 15-cycle Si0.7Ge0.3/Si multilayer structure and the associated etching effects, using simulation and experimentation. The simulation predicts the random effect of lateral etching depth and the asymmetric effect of silicon nanosheet damage on the edge, both of which are verified by experiments. Furthermore, the study experimentally investigates the influence and mechanism of pressure, power, and other parameters on the etching results. Research on these etching effects and mechanisms will provide important points of reference for the dry selective etching of Si0.7Ge0.3 in GAA structures.

Acute kidney injury (AKI) is a frequently occurring severe disease with high mortality. Cystatin C (Cys-C), as a biomarker of early kidney failure, can be used to detect and prevent acute renal injury. In this paper, a biosensor based on a silicon nanowire field-effect transistor (SiNW FET) was studied for the quantitative detection of Cys-C. Based on the spacer image transfer (SIT) processes and channel doping optimization for higher sensitivity, a wafer-scale, highly controllable SiNW FET was designed and fabricated with a 13.5 nm SiNW. In order to improve the specificity, Cys-C antibodies were modified on the oxide layer of the SiNW surface by oxygen plasma treatment and silanization. Furthermore, a polydimethylsiloxane (PDMS) microchannel was involved in improving the effectiveness and stability of detection. The experimental results show that the SiNW FET sensors realize the lower limit of detection (LOD) of 0.25 ag/mL and have a good linear correlation in the range of Cys-C concentration from 1 ag/mL to 10 pg/mL, exhibiting its great potential in the future real-time application.

Abstract A charge‐trapping memory (CTM) field effect transistor (FET) featured with an Hf1.5Gd2O6 charge trapping layer and thin MoS2 channel are fabricated. Benefit from high defect densities of the Hf1.5Gd2O6 film, large memory windows are achieved under low operating voltages (2.3 V@4 V, 3.1 V@5 V and 3.6 V@6 V), which distinctly outperform previously reported CTMs. In addition, high programming/erase (P/E) speeds, good data retention and endurance characteristics are experimentally demonstrated. The results demonstrate a feasibility of CTM FET with an HfGdO charge trapping layer and thin MoS2 channel for ultra‐low power memory devices application.

Developing novel silicon quantum dots (Si-QDs) on conventional CMOS process is one of the most important technologies in Si quantum computing to realize multi-bit integration with a large scale. In this paper, an analysis model based on master equation and realized by Python code is established to predict and optimize the performance of fabricated diamond channel Si-QDs for potential circuit applications. The model can fast describe the I-V characteristics of devices both in qualitative and semi quantitative method. The inherent tunneling process of Si-QDs can be well simulated by introducing additional parameters and the contribution of neighboring states can be analyzed by setting global parameters. In addition, the calculation speed and accuracy can be readily balanced by modifying the setting parameters. The simulation results of the model are in good agreement with the experimental results at low temperature, which lays a foundation for the performance prediction, structure and process optimization of the Si-QDs for a large scale circuit applications.

In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (−2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.

In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate stack, fresh interface quality, threshold voltage shift ( ${\Delta }$ V $_{T}$ ), pre-existing traps ( ${\Delta } {N} _{\mathrm {HT}}$ ), generated traps, and their relative contributions were studied. The time exponents of ${\Delta }$ V $_{T}$ , the impacts of stress bias and temperature on NBTI degradation, and the recovery kinetics of the generated traps were analyzed. For devices with a B2H6-based W-filling metal, a 34% reduction in the fresh interface states, reduced ${\Delta }$ V $_{T}$ , and a 29% improvement in the operation overdrive voltage could be achieved by optimizing the annealing conditions. The NBTI is alleviated mainly because of the reduction in the generated traps, while the energy distribution of ${\Delta } {N} _{\mathrm {HT}}$ is insensitive to the annealing conditions. Furthermore, the relative contribution of the generated bulk insulator traps to the total number of generated traps could be reduced by optimizing the annealing conditions.

In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N+ pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of 40 μA/μm, a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with VDS = VGS = 1 V at room temperature. It is shown that once the trap assisted tunneling is suppressed at the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decade was obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application.

Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devices with different structures and parameters on TID effects, such as buried oxide (BOX) layer thickness, buried Si3N4 layer, and electron traps. First, we construct four types of UTB-FDSOI N-type metal-oxide semiconductor (NMOS) devices numerically, in which the novel device features a buried silicon-oxidenitride-oxide-silicon (SONOS) structure. Then, the transfer characteristics and trapped charge distribution of these devices are studied under different irradiation doses. It is known that a thinner BOX layer could lead to slighter TID effects, and the buried nitride layer and the electron traps could reduce the TID-induced leakage current (Ioff). Employing these optimization structures for TID effects hardness, the innovative transistor shows much better resistance against TID effects compared to the conventional FDSOI transistors. In addition, the threshold voltage of the novel device could be increased by applying appropriate bias conditions, similar to those of programming SONOS memory, so that the Ioff caused by TID irradiation further decreases. These results provide useful guidance for designers to achieve TID effects mitigation of SOI devices.

Landslides are one of the most prevalent environmental disasters in the Hengduan Mountain Region. Landslides lead to severe economic damage and property loss, as well as fatalities. Furthermore, they tend to increase in the context of climate change. The purpose of this study is to comprehensively assess landslide susceptibility across the Hengduan Mountain Region in southwest China. Specifically, the analysis is focused on the eastern boundary of the Tibetan Plateau within the context of future climate change scenarios, which are based on the latest Coupled Model Intercomparison Project Phase 6 (CMIP6) global climate model ensemble. The Generalized Additive Model (GAM), Random Forest (RF), and Light Gradient Boosting Machine (LightGBM) were selected in order to map landslide susceptibility within the context of 1.5–4.0 °C warming scenarios. This was achieved by considering the changes in extreme rainfall that exceeded the landslide triggering thresholds. The results show that the frequency over extreme rainfall thresholds (FOERT) tend to increase in conjunction with warming targets, thereby ranging from 2.3/a (at a 1.5 °C warming) to 9.0/a (at a 4.0 °C warming) on average. Such elevated extreme precipitation events contribute to an increase in projected future zones of high landslide susceptibility when compared to the historical baseline period ranging from −1.2% (at a 1.5 °C warming) to 4.0% (at a 4.0 °C warming) using different machine learning models. Moreover, the extent of high susceptibility zones increases more significantly in the context of 4.0 °C warming when compared to the historical baseline results. These results indicate the importance of limiting the global temperature rise to 1.5 as well as 2 °C. The high landslide susceptibility zones estimated by the CMIP6 multi-models ensemble are mainly located in the central and southeastern regions of the Hengduan Mountain Region. The possible changes in terms of introducing extreme precipitation in order to assess landslide susceptibility in the context of climate change that is proposed in this study may be further applied to additional study areas. These projections under different targets can provide scientific guidelines for the purposes of the development of climate change adaptation strategies.

To allow the use of molybdenum disulfide (MoS2) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS2 transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is presented. The fabrication technology of the ultra-small MoS2 device shows fully process compatibility with conventional Si-FinFET process flow and it is also the first time to realize the large-scale fabrication of the arrayed MoS2 transistors with 10-nm gate lengths. The fabricated ultrathin transistors, consisting of 10-nm gate length and 0.7-nm monolayer CVD MoS2, exhibit good switching characteristics and the average drain current on/off ratio reaches to over 106. This technology provides a promising approach for future CMOS scaling with large scale new 2-D material transistors.

The electronic properties and transport properties of MoTe2/SnS2 heterostructure Tunneling FETs are investigated by the density functional theory coupled with non-equilibrium Green’s function method. Two dimensional (2D) monolayer MoTe2 and SnS2 are combined to a vertical van der Waals heterojunction. A small staggered band gap is formed in the overlap region, while larger gaps remain in the underlap source and drain regions of monolayer MoTe2 and SnS2 respectively. Such a type-II heterojunction is favorable for tunneling FET. Furthermore, we suggest short stack length and large gate-to-drain overlap to enhance the on-state current suppress the leakage current respectively. The numerical results show that at a low drain to source voltage Vds = 0.05V, On/Off current ratio can reach 108 and the On-state currents is over 20 μA/μm for n-type devices. Our results present that van der Waals heterostructure TFETs can be potential candidate as next generation ultra-steep subthreshold and low-power electronic applications.

In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (≥1000 °C) process flow. Schottky S/D PMOS exhibits an ON-state current (ION) of 76.07 μA/μm and ON-state to OFF-state current ratio (ION/IOFF) of 7 × 105, and those for NMOS are 48.57 μA/μm and 1 × 106. The CMOS inverter shows a voltage gain of 18V/V, a noise margin for high (NMH) of 0.17 V and for low (NML) of 0.43 V, with power consumption less than 0.9 μW at VDD of 0.8 V. Full functionality of CMOS ring oscillators (RO) are further demonstrated.

In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si0.7Ge0.3 channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si0.7Ge0.3/Si film is achieved by optimizing the epitaxial growth process and a vertical profile of stacked Si0.7Ge0.3/Si fin is attained by further optimizing the etching process under the HBr/He/O2 plasma. Moreover, a novel ACT@SG-201 solution without any dilution at the temperature of 40 °C is chosen as the optimal etching solution for the release process of Si0.7Ge0.3 channel. As a result, the selectivity of Si to Si0.7Ge0.3 can reach 32.84 with a signature of “rectangular” Si0.7Ge0.3 extremities after channel release. Based on these newly developed processes, a 4-levels vertically stacked Si0.7Ge0.3 nanowires gate-all-around device is prepared successfully. An excellent subthreshold slope of 77 mV/dec, drain induced barrier-lowering of 19 mV/V, Ion/Ioff ratio of 9 × 105 and maximum of transconductance of ~83.35 μS/μm are demonstrated. However, its driven current is only ~38.6 μA/μm under VDS = VGS = −0.8 V due to its large resistance of source and drain (9.2 × 105 Ω). Therefore, a source and drain silicide process is implemented and its driven current can increase to 258.6 μA/μm (about 6.7 times) due to the decrease of resistance of source and drain to 6.4 × 104 Ω. Meanwhile, it is found that a slight increase of leakage after the silicide process online results in a slight deterioration of the subthreshold slope and Ion/Ioff ratio. Its leakage performance needs to be further improved through the co-optimization of source and drain implantation and silicide process in the future.

The rapid assessment of building damage in earthquake-stricken areas is of paramount importance for emergency response. The development of remote sensing technology has aided in deriving reliable and precise building damage assessments of extensive areas following disasters. It is well documented that convolutional neural network methods have superior performance in earthquake building damage assessment compared with traditional machine learning methods. However, deep learning models require a large number of samples, and sufficient numbers of samples are usually not available in the newly earthquake-stricken areas rapidly enough. At the same time, the historical samples inevitably differ from the new earthquake-affected areas due to the discrepancy of regional building characteristics. For this purpose, this study proposes a data transfer algorithm for evaluating the impact of a single historical training sample on the model performance. Then, beneficial samples are selected to transfer knowledge from the historical data for facilitating the calibration of the new model. Four models are designed with two earthquake damage building datasets and the performance of the models is compared and evaluated. The results show that the data transfer algorithm proposed in this work improves the reliability of the building damage assessment model significantly by filtering samples from the historical data that are suitable for the new task. The performance of the model built based on the data transfer method on the test set of new earthquakes task is approximately 8% higher in overall accuracy compared with the model trained directly with the new earthquake samples when the training data for the new task is only 10% of the historical data and is operating under the objective of four classes of building damage. The proposed data transfer algorithm has effectively enhanced the precision of the seismic building damage assessment in a data-limited context. Thus, it could be applicable to the building damage assessment of new disasters.

We present a comprehensive theoretical investigation of the quantum confinement limited mobility in the Si1-xGex-channel gate-all-around nanosheet field effect transistor for 5-nm node. The study encompasses physics-based quantum mechanical models both for P and NMOS with specified channel/wafer orientations and channel thicknesses: (1) k.p model with Poisson solver for band structures, bandgap variations, and confined charge distributions; (2) Kubo-greenwood model for low field mobility with considering surface roughness and stress; (3) multisub-band Boltzmann transport equation based on a state-of-the-art phase space approach is employed to evaluate device IV characteristics; and (4) the threshold voltage (VT) variations with different channel/wafer orientations are also evaluated. Our simulation study shows that {110} wafer Ge channel can be an attractive option for 5-nm node pMOS, and Si is still promising for nMOS due to strong quantum confinement in Ge channel.

The degradation of InSe film and its impact on field effect transistors are investigated. After the exposure to atmospheric environment, 2D InSe flakes produce irreversible degradation that cannot be stopped by the passivation layer of h-BN, causing a rapid decrease for InSe FETs performance, which is attributed to the large number of traps formed by the oxidation of 2D InSe and adsorption to impurities. The residual photoresist in lithography can cause unwanted doping to the material and reduce the performance of the device. To avoid contamination, a high-performance InSe FET is achieved by a using hard shadow mask instead of the lithography process. The high-quality channel surface is manifested by the hysteresis of the transfer characteristic curve. The hysteresis of InSe FET is less than 0.1 V at Vd of 0.2, 0.5, and 1 V. And a high on/off ratio of 1.25 × 108 is achieved, as well relative high Ion of 1.98 × 10−4 A and low SS of 70.4 mV/dec at Vd = 1 V are obtained, demonstrating the potential for InSe high-performance logic device.

Abstract In this paper, pMOSFETs featuring atomic layer deposition (ALD) tungsten (W) using SiH4 and B2H6 precursors in 22 nm node CMOS technology were investigated. It is found that, in terms of threshold voltage, driving capability, carrier mobility, and the control of short-channel effects, the performance of devices featuring ALD W using SiH4 is superior to that of devices featuring ALD W using B2H6. This disparity in device performance results from different metal gate-induced strain from ALD W using SiH4 and B2H6 precursors, i.e. tensile stresses for SiH4 (~2.4 GPa) and for B2H6 (~0.9 GPa).

HfO2-based ferroelectric materials have been widely studied for their application in ferroelectric FETs, which are compatible with conventional CMOS processes; however, problems with the material’s inherent fatigue properties have limited its potential for device application. This paper systematically investigates the effects of tensile stress and annealing temperature on the endurance and ferroelectric properties faced by Zr-doped HfO2 ferroelectric film. The remnant polarization (Pr) shows an increasing trend with annealing temperature, while the change in the coercive electric field (Ec) is not obvious in terms of the relationship with tensile stress or annealing temperature. In addition, the application of tensile stress does help to improve the endurance characteristics by about two orders of magnitude for the ferroelectric material, and the endurance properties show a tendency to be negatively correlated with annealing temperature. Overall, although the effect of stress on the ferroelectricity of a HZO material is not obvious, it has a great influence on its endurance properties and can optimize the endurance of the material, and ferroelectricity exhibits a higher dependence on temperature. The optimization of the endurance properties of HZO materials by stress can facilitate their development and application in future integrated circuit technology.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

In this paper, the poly-Si nanowire (NW) field-effect transistor (FET) sensor arrays were fabricated by adopting low-temperature annealing (600 °C/30 s) and feasible spacer image transfer (SIT) processes for future monolithic three-dimensional integrated circuits (3D-ICs) applications. Compared with other fabrication methods of poly-Si NW sensors, the SIT process exhibits the characteristics of highly uniform poly-Si NW arrays with well-controlled morphology (about 25 nm in width and 35 nm in length). Conventional metal silicide and implantation techniques were introduced to reduce the parasitic resistance of source and drain (SD) and improve the conductivity. Therefore, the obtained sensors exhibit >106 switching ratios and 965 mV/dec subthreshold swing (SS), which exhibits similar results compared with that of SOI Si NW sensors. However, the poly-Si NW FET sensors show the Vth shift as high as about 178 ± 1 mV/pH, which is five times larger than that of the SOI Si NW sensors. The fabricated poly-Si NW sensors with 600 °C/30 s processing temperature and good device performance provide feasibility for future monolithic three-dimensional integrated circuit (3D-IC) applications.

Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.