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The determination of charged particle trajectories in collisions at the CERN Large Hadron Collider (LHC) is an important but challenging problem, especially in the high interaction density conditions expected during the future high-luminosity phase of the LHC (HL-LHC). Graph neural networks (GNNs) are a type of geometric deep learning algorithm that has successfully been applied to this task by embedding tracker data as a graph-nodes represent hits, while edges represent possible track segments-and classifying the edges as true or fake track segments. However, their study in hardware- or software-based trigger applications has been limited due to their large computational cost. In this paper, we introduce an automated translation workflow, integrated into a broader tool called hls4ml, for converting GNNs into firmware for field-programmable gate arrays (FPGAs). We use this translation tool to implement GNNs for charged particle tracking, trained using the TrackML challenge dataset, on FPGAs with designs targeting different graph sizes, task complexites, and latency/throughput requirements. This work could enable the inclusion of charged particle tracking GNNs at the trigger level for HL-LHC experiments.

The good mechanical properties of metal nitrides make them ideal surface coatings for cutting tools and mold components. Conventional TiN coatings have largely been replaced by AlTiN due to their superior mechanical properties and resistance to high temperatures. In this study, we investigated the application of bias voltage to the substrate to enhance ion bombardment during the synthesis of protective AlTiN coatings using high-power impulse magnetron sputtering (HiPIMS) with synchronous trigger-direct current (ST-DC) bias voltage. The ST-DC parameters included the duty cycle duration (3%, 6%, 12%, 18%) and turn-on time, which included synchronous (TD0) or a trigger delay of 50 μs (TD50). Scanning electron microscope images revealed that the highest deposition rate (22.1 nm/min) was achieved using TD50 with a duty cycle of 3%. The results obtained using an electron probe microanalyzer and X-ray diffractometer revealed the formation of an h-AlN structure when the Al/Ti ratio was between 0.71 and 0.74. Transmission electron microscopy and nanoindentation results revealed that transforming DC bias into synchronous bias to boost the bias output time (i.e., increasing the duty cycle) increased AlTiN grain refinement (from ~100 nm to ~55 nm) with a corresponding increase in hardness (from 22.7 GPa to 24.7 GPa) as well as an increase in residual stress within the AlTiN coating (from 0.16 GPa to −51 GPa). The excellent adhesion performance of the coatings provided further evidence indicating the importance of duty cycle and trigger delay when using pulsed-DC bias in HiPIMS. [ABSTRACT FROM AUTHOR]

A conventional latch-type sense amplifier in a static random access memory (SRAM) could trigger sensing failure under severe process variation. On the other hand, a traditional current-mirror sense amplifier could consume too much power. To strike a good balance, this paper presents an automatic-power-down (APD) sense amplifier, which can avoid sensing failure while keeping the power dissipation low. In this scheme, the operation window of the sense amplifier is adaptive to the real silicon speed of its associated column through Schmitt--Trigger-based dual-[V.sub.HL] APD circuitry. A 64-kb SRAM design using the proposed technique in a 22-nm predictive technology model demonstrates that a power savings of 28%-87% over the traditional current-mirror sense amplifier is achievable. Index Terms--Automatic-power-down (APD) circuitry, sense amplifier, static random access memory (SRAM).

In this brief, we present a robust new paradigm for diagnosing a scan chain with multiple faults that could have different fault types. As compared to previous methods, the major advantage of ours is the ability to not only target mixed multiple types of timing faults in the same scan chain but also tolerate non-ideal conditions, e.g., when these faults only manifest themselves intermittently. Unlike the previous matching-based algorithms, we formulate the diagnosis problem as an image recovery process featuring a dynamic windowing technique and a running sequence handling technique. Experimental results on a number of real designs show that this paradigm can successfully deal with some situations beyond existing methods. Index Terms--Fault diagnosis, scan chain.

A delay-locked loop (DLL) circuit is often useful for the clock synchronization in a chip incorporating multiple functional dies. In this work, we present a process-resilient fault-tolerant DLL design. We will first show that a naïve triple-module redundancy (TMR) technique cannot work well unless with a simple yet powerful static timing correction scheme to nullify the adversary effect caused by the voter circuit’s delay. Furthermore, we enhance it with a dynamic scheme so that the overall performance is immune to process variation. Through the proposed schemes, the maximum phase error over 1000 clock cycles between the DLL’s input and output clock signals after locking, which is often considered as the most important performance metric, can be reduced tremendously from 130 ps using only naïve TMR to 20 ps using static timing correction, and then further down to 11 ps using the dynamic timing correction. [ABSTRACT FROM AUTHOR]