A resilient and power-efficient automatic-power-down sense amplifier for SRAM design

A conventional latch-type sense amplifier in a static random access memory (SRAM) could trigger sensing failure under severe process variation. On the other hand, a traditional current-mirror sense amplifier could consume too much power. To strike a good balance, this paper presents an automatic-power-down (APD) sense amplifier, which can avoid sensing failure while keeping the power dissipation low. In this scheme, the operation window of the sense amplifier is adaptive to the real silicon speed of its associated column through Schmitt--Trigger-based dual-[V.sub.HL] APD circuitry. A 64-kb SRAM design using the proposed technique in a 22-nm predictive technology model demonstrates that a power savings of 28%-87% over the traditional current-mirror sense amplifier is achievable. Index Terms--Automatic-power-down (APD) circuitry, sense amplifier, static random access memory (SRAM).