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An RF electrostatic discharge (ESD) protection for millimeter-wave (MMW) regime applied to a 60-GHz low-noise amplifier (LNA) in mixed-signal and RF purpose 0.13-[micro]m CMOS technology is demonstrated in this paper. The measured results show that this chip achieves a small signal gain of 20.4 dB and a noise figure (NF) of 8.7 dB at 60 GHz with 65-mW dc power consumption. Without ESD protection, the LNA exhibits a gain of 20.2 dB and an NF of 7.2 dB at 60 GHz. This ESD protection using an impedance isolation method to minimize the RF performance degradation sustains 6.5-kV voltage level of the human body model on the diode and 1.5 kV on the core circuit, which is much higher than that without ESD protection ( Index Terms--CMOS integrated circuits (ICs), low-noise amplifiers (LNAs), millimeter-wave (MMW) circuits, RF electrostatic discharge (ESD) protection.

To reach high energy density and excellent cycle stability, an asymmetric supercapacitor device combining a high-power electric double-layer capacitor (EDLC) anode and high energy density battery-type cathode has been designed and fabricated. A binder-free strategy was used to prepare cathode by coating graphene (G) on Ni foam (Ni), then electrodepositing MnO2, followed by calcination process. The potentiodynamic (PD) electrodeposition cycles of MnO2 onto graphene significantly impact the electrochemical properties. Benefiting from the hierarchical structure and binder-free process of the designed 75 C/G/Ni hybrid cathode, potentiostatic (PS) electrodeposition followed by PD electrodeposition for 75 cycles demonstrates a high specific capacitance of 691 F g−1 at 2 A g−1. The enhanced capacitive performance can be attributed to the synergistic effect between MnO2 nanosheets and graphene, in which graphene can serve as ideal support matrix and conductive channels. Furthermore, an asymmetric supercapacitor was fabricated with 75 C/G/Ni and (G + AC)/Ni as the cathode and anode, respectively, and a carboxymethyl cellulose–potassium hydroxide (CMC-KOH) gel electrolyte. The 75 C/G/Ni//(G + AC)/Ni asymmetric supercapacitor (ASC) exhibits a maximum energy density of 43 kW kg−1 at a power density of 302 W kg−1 with a potential window of 1.6 V and maintains good cycling stability of 88% capacitance retention at 2 A g−1 (over 5000 cycles). Four solid-state asymmetric supercapacitors stack connected in series display an effective 5.0 V working potential to increase the voltage and output energy as a device. The device was charged using a 18,650 Li battery with a voltage of +3.8 V for 30 s and discharged six white LEDs for 20 min. The facile fabrication and remarkable capacitive performance of the MnO2/G/Ni hybrid make it a promising electrode candidate in electrochemical energy conversion/storage devices. [ABSTRACT FROM AUTHOR]

A new distributed amplifier (DA) topology is proposed, which is a combination of the conventional DA and the cascaded single-stage DA. This DA topology can provide wide bandwidth with considerations of the gain, noise figure (NF), and output power simultaneously, and requires reasonable dc power consumption. In this paper, two termination methods of this combination are investigated. From the measurements, the first DA proposed by Chen in 2011 has a small-signal gain of 20.5 dB, a 3-dB bandwidth of 35 GHz, and a gain-bandwidth (GBW) product of 371 GHz. The maximum output power at 1-dB output compression point (OP1~{dB}) is 8.6 dBm and the NF is between 6.8–8 dB at frequencies lower than 18 GHz. The chip size, including testing pads, is only \ 0.78 mm^2, and the ratio of the GBW to chip size is \476 GHz/mm^2. The second DA has a small-signal gain of 24 dB, a 3-dB bandwidth of 33 GHz, and a GBW product of 523 GHz. The maximum OP1~{dB} is 9 dBm and the NF is between 6.5–7.5 dB at frequencies lower than 18 GHz. The chip size including testing pads is only \ 0.83 mm^2, and the ratio of the GBW to chip size is \630 GHz/\ mm^2. To the authors' knowledge, the second circuit has the highest ratio of GBW to chip area and the highest figure-of-merit in \0.18- \mu\ m CMOS, and it has a comparable performance with other DAs in advanced process. [ABSTRACT FROM AUTHOR]

This letter demonstrates a 22–31 GHz CMOS distributed amplifier (DA) based on high-pass transmission lines. Unlike the low-pass DA, the circuit can be smaller since it does not need extra drain bias circuits. This DA has a maximum output power of 12 dBm, a maximum OP1dB of 6.5 dBm, and a small signal gain of 6.4 dB. The chip occupies a miniature area of 0.28 mm^2 including the pads and the core area is only 0.17 mm^2. [ABSTRACT FROM PUBLISHER]