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We report on the successful integration of multiple atomically thin horizontal heterojunctions (HJs) epitaxially grown via metal organic chemical vapor deposition inside a confined template of diel...

The selective area growth technique, confined epitaxial lateral overgrowth (CELO), enables the growth of lateral III-V heterojunctions integrated on mismatched substrates. In CELO, effective control of facet shapes, as well as defect-free growths are essential to fabricating high-quality nanostructures with custom geometries. Here, the effects of growth temperature, V/III ratio, template alignments, and substrate orientations on the observed facets and defect densities in CELO grown InP and related materials on InP substrates are investigated. The nanostructure facets and defects are determined using a combination of plan-view and cross-sectional transmission electron microscopy. For homoepitaxial CELO growth on InP (100) substrates, growth temperatures below $575{\phantom{\rule{0.16em}{0ex}}}^{\ensuremath{\circ}}\mathrm{C}$, and high V/III ratios of 450 aid in increasing the surface areas of the {111}B facets, while reducing defect densities. Further, by changing template alignments, the effective areas of overgrowth can be tuned, and defects can be lowered, with templates aligned along $[0\overline{1}0]$ yielding the largest defect-free areas. By aligning templates in the $[\overline{1}10]$ orientation on a (110) InP substrate, near defect-free overgrowth with perfectly flat perpendicular single ($1\overline{1}$ 0) facets can be achieved. This is an essential feature to enable the growth of lateral III-V heterojunctions, as is demonstrated by growing InP/InGaAs CELO heterojunctions with {110} facets.

Triple heterojunction (THJ) tunneling field-effect transistors (TFETs) have been proposed to resolve the low ON-current challenge of TFETs. However, the design space for THJ-TFETs is limited by fabrication challenges with respect to device dimensions and material interfaces. This work shows that the original THJ-TFET design with 12-nm body thickness has poor performance because its subthreshold swing (SS) is 50 mV/decade and the ON-current is only $6~\mu A/\mu m$ . To improve the performance, the doping profile of THJ-TFET is engineered to boost the resonant tunneling efficiency. The proposed THJ-TFET design shows an SS of 40 mV/decade over four orders of drain current and an ON-current of $325~\mu A/\mu m$ with ${V}_{\textit {GS}} =0.3$ V. Since THJ-TFETs have multiple quantum wells and material interfaces in the tunneling junction, quantum transport simulations in such devices are complicated. State-of-the-art mode-space quantum transport simulation, including the effect of thermalization and scattering, is employed in this work to optimize THJ-TFET design.

We report ${L}_{g}= 30$ nm InAs-channel MOSFETs exhibiting 420 GHz ${f}_{\textit {max}}$ , record for a III-V MOSFET, and 357 GHz ${f}_{t}$ . The device incorporates a 5-nm strained InAs channel grown on an InP substrate. To reduce the parasitic gate-source and gate-drain capacitances, regrown lateral access regions increase the separations between the gate and the N+ source and drain; modulation doping within these access regions provides a low associated series resistance, enabling high ${g}_{m}$ . The 30 nm ${L}_{g}$ device shows an 1.5 mS/ $\mu \text{m}$ DC peak extrinsic ${g}_{m}$ at ${V}_{\textit {DS}} = 0.5$ V and ${V}_{\textit {GS}} = 0.3$ V, 91% of the value (1.65 mS/ $\mu \text{m}$ ) extracted from 10 MHz RF measurements, indicating a low DC-RF dispersion.

InP channel planar and vertical MOSFETs utilizing atomic layer deposition of a TiN/Ru gate are fabricated. The performance of the TiN/Ru gate is compared to a Ru-only gate based on the C–V characteristics of MOS (metal–oxide–semiconductor) capacitors and peak transconductance ( gm) and subthreshold swing ( SS) in planar MOSFETs. Compared to devices with the conventional Ni/Au gate metal, these have a 70 mV/dec SS [Tseng et al., in Device Research Conference (IEEE, 2019), pp. 183–184.] and a long gate length; TiN/Ru gate devices exhibit an average 68 mV/dec SS, a record low value of InP, suggesting a high quality, low-damage high-k/InP interface. A record high peak gm of 0.75 mS/μm at VDS = 0.6 V on an InP channel is achieved in a planar gate length ( Lg)= 80 nm device. A vertical MOSFET shows a reasonably conformal Ru coverage of the vertical fin and a high 0.42 mS/μm peak gm for a Lg = 50 nm device. The results of planar and vertical MOSFETs show that TiN/Ru gate metallization via atomic layer deposition is promising for non-planar III–V MOS devices.

We report DC results from a $W_{e}=100\mathrm{nm\ InP}/\mathrm{InGaAs}$ DHBT technology with a self-aligned MOCVD regrown GaAs extrinsic base providing low base access resistance $R_{bb}$ while maintaining acceptable DC current gain $\beta$ . A $0.09\times 5\mu \mathrm{m}^{2}$ transistor exhibits a base contact resistivity $\rho_{c}=1\Omega-\mu \mathrm{m}^{2}$ , and a peak $\beta\sim 15$ . The HBTs exhibit a common-emitter breakdown voltage $BV_{CEO}=3.6\mathrm{V}(J_{C}=10\mu \mathrm{A}/\mu \mathrm{m}^{2})$ . According to the general scaling law for InP HBTs in [1], the low $\rho_{c}$ meets the requirement for $f_{max}=2.8\mathrm{THz}$ operation.

The influence of growth conditions on the incorporation and activation of Mg in GaN grown by plasma-assisted molecular beam epitaxy at high growth temperature (>700 °C) is presented. It is found that the highest Mg incorporation with optimized electrical properties is highly sensitive both to the Mg/Ga flux ratio and III/V flux ratio. A maximum Mg activation of ~5% can be achieved at a growth temperature of 750 °C. The lowest resistivity achieved is 0.56 Ω-cm which is associated with a high hole mobility of 6.42 cm 2 /V-s and a moderately high hole concentration of 1.7×10 18 cm −3 . Although the highest hole concentration achieved in a sample grown under a low III/V flux ratio and a high Mg/Ga flux ratio reaches 7.5×10 18 cm −3 , the mobility is suffered due to the formation of defects by the excess Mg. In addition, we show that modulated beam growth methods do not enhance Mg incorporation at high growth temperature in contrast to those grown at a low temperature of 500 °C (Appl. Phys. Lett. 93, 172112, Namkoong et al., 2008 [19]).

Selectively growing epitaxial material in confined dielectric structures has been explored recently as a pathway to integrate highly mismatched materials on silicon substrates. This approach involves the fabrication of a channel-like structure of dielectric material that from the growth atmosphere reaches down to a small exposed area of the substrate where subsequent growth via metal organic chemical vapor deposition (MOCVD) initiates. The technique, referred to as template assisted selective epitaxy, can also enable the development of novel nanoscale photonic and electronic device structures because of its ability to allow epitaxy to progress in a direction, final size, and aspect ratio defined by the dielectric template, and allows integration of horizontal heterojunction inside the channel. To date, most confined epitaxy work has been detailed on silicon. Due to the reduced chemical and thermal stability of InP compared to Si, additional steps for surface preparation are required. In this work, two different fabrication routes are described on InP substrates: one involving amorphous silicon as a sacrificial layer and deposited SiO2 as top oxide, while the other involves spin coated photoresist and hydrogen-silsesquioxane sourced SiOx. Both routes, leading to similar template structures, are demonstrated and discussed. Homoepitaxy of InP in both types of templates and the integration of an InAs horizontal heterojunction are demonstrated via MOCVD. An increase in growth rate with decreasing template length, increasing template width, and decreasing pattern density is observed.Selectively growing epitaxial material in confined dielectric structures has been explored recently as a pathway to integrate highly mismatched materials on silicon substrates. This approach involves the fabrication of a channel-like structure of dielectric material that from the growth atmosphere reaches down to a small exposed area of the substrate where subsequent growth via metal organic chemical vapor deposition (MOCVD) initiates. The technique, referred to as template assisted selective epitaxy, can also enable the development of novel nanoscale photonic and electronic device structures because of its ability to allow epitaxy to progress in a direction, final size, and aspect ratio defined by the dielectric template, and allows integration of horizontal heterojunction inside the channel. To date, most confined epitaxy work has been detailed on silicon. Due to the reduced chemical and thermal stability of InP compared to Si, additional steps for surface preparation are required. In this work, two dif...

GaN-based Schottky barrier diodes (SBDs) with single-crystal Al barriers grown by plasma-assisted molecular beam epitaxy are fabricated. Examined using in-situ reflection high-energy electron diffractions, ex-situ high-resolution x-ray diffractions, and high-resolution transmission electron microscopy, it is determined that epitaxial Al grows with its [111] axis coincident with the [0001] axis of the GaN substrate without rotation. In fabricated SBDs, a 0.2 V barrier height enhancement and 2 orders of magnitude reduction in leakage current are observed in single crystal Al/GaN SBDs compared to conventional thermal deposited Al/GaN SBDs. The strain induced piezoelectric field is determined to be the major source of the observed device performance enhancements.