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Crosstalk repair by gate sizing often increases the noise on adjacent wires, and results in cyclical iterations of noise repair. We propose a Delayed Actively Body-bias Controlled (D-ABC) SOI scheme for crosstalk noise repair by providing delayed forward bias to drivers. The delay between gate and body suppresses the crosstalk noise on adjacent wires. The proposed D-ABC SOI scheme has reduced the crosstalk noise by 48.5%, with 4.3% increase in the crosstalk noise on adjacent wires.

In MTCMOS, the circuit state should be preserved for state retentive sleep, and the virtual power/ground rails clamp (VRC) scheme is an effective method for this purpose. Our approach realizes the voltage clamp function without additional devices like diodes, by feeding the virtual ground voltage back into a sleep signal. There are also other effects; cutting off the leak current of the sleep buffer, and charge recycling of sleep signal node. We have achieved a 19.7% lower power consumption and a 5.4% cell area reduction.

We propose a test structure for systematic variation measurement over the whole shot and wafer area at a 45 nm process node. With this structure, we found that the systematic variation had two kinds of site dependence, one is a wafer scale and the other is a shot scale component. Additionally, the Die-to-Die and Within-Die variations for any chip size are calculated. Then, the systematic variation component has the correlation length more than 16mm. This shows that it is necessary to take into consideration the Within-Die variation according to the Die size.

An on-chip digital Ids measurement method is proposed in this report. In the proposed method, Ids is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS Ids (Idn) and PMOS Ids (Idp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first Ids calculated from measured frequencies, and the second Ids directly measured for reference, was analyzed. The standard deviations of the mismatch error in Idn and Idp are 1.64% and 1.09%, respectively. The margin of 3sigma is within 5% which is our target tolerance for a practical application.

This paper proposes on-chip leakage monitor circuit to scan optimal reversed body-biasing voltage (VBB) at which leakage current becomes minimal under gate induced drain leakage (GIDL) effect. The proposed circuit determines optimal VBB from the differential measurement of two replica circuit without absolute leakage current measurement. We fabricated this leakage monitor circuit in a 45 nm-CMOS process. Measurement results shows 0.1 V resolution of VBB optimization.

In this paper, we propose a new technique for higher circuit speed without increase in leakage current by using active body-bias controlling technique. Conventional body-bias controlling techniques face difficulties, such as long transition time of body voltage and large area penalty. To overcome these issues, we propose a Charge Recycling Active Body-bias Controlled (CRABC) circuit scheme on SOI which enables quick control of body voltage by using simple additional circuit. The SPICE simulation results have shown that CRABC shortens delay time by 20 %, and transition time for controlling body-bias by 98 %.

A wide lock-in range PLL using a self-calibrating technique is proposed. This technique realizes a wide lock-in range and good jitter characteristics by performing the digital calibration at the start of the operation. However, self-calibration with a large number of digital control steps increases the test costs and circuit scale. In this paper, by estimating the margin for self-calibrating operation, the minimum number of digital control steps was determined. A PLL with a low test cost, a wide lock-in range and low jitter was designed and implemented using a 0.15 mum 1.5 V CMOS process. The measured PLL lock-in range is 80 MHz - 630 MHz with four digital calibration steps. The peak-to-peak jitter at 380 MHz is 100 ps

We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 /spl mu/m CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.

A 0.5 /spl mu/m CMOS 622Mb/s 32/spl times/8 shared-buffer ATM switch chip set consists ofa buffer LSI and a control LSI. It has a 768-cell on-chip buffer controlled by a searchable address queue running at 400 MHz with a double-edge triggered hand-shake circuit. The switch realizes 5 Gb/s total throughput with 8-level delay and 4-level cell-loss priorities for multimedia communications. A funnel structure enables a scalable switch size. 32 bit/frame synchronizers are integrated for all input channels.