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Degradation of (Ba,Sr)TiO3 during a forming gas anneal was examined and the effect of a SiO2 capped (Ba,Sr)RuO3 electrode was studied. All the samples were prepared by a rf magnetron sputtering technique and the forming gas (10% H2+90% N2) anneal was carried out at 400 °C for 30 min. The (Ba,Sr)RuO3 film directly exposed to H2 ambient was damaged severely, which resulted in the reduction and phase separation into BaO and Ru. On the other hand, the SiO2 capped (Ba,Sr)RuO3 film was not damaged during H2 annealing. By adopting the SiO2 capped (Ba,Sr)RuO3 as an electrode of (Ba,Sr)TiO3, the degradation of (Ba,Sr)TiO3 could be inhibited. SiO2 capping also decreased the extent of the reduction of a Pt/(Ba,Sr)TiO3/Pt structured capacitor, which is known to degrade dramatically. It is believed that the major cause of the tolerance to the forming gas anneal is the blocking capability of SiO2 against the diffusion of reaction products such as H2O.

(Ba,Sr)RuO 3 films have been tailored as an electrode for (Ba,Sr)TiO 3 which is a promising material for the high dielectric in ULSI DRAM. In this study, BSR conductive oxide film was deposited on 4-inch Si-wafer by metal organic chemical vapor deposition (MOCVD) using single cocktail source for the practical device application. Liquid delivery system (LDS) and vaporization cell were utilized for the delivery and vaporization of single cocktail source, respectively. The source feeding rate was controlled by liquid mass flow controller(LMFC). Ba(METHD) 2 , Sr(METHD) 2 , Ru(METHD) 3 precursors and solvent [n-butylacetate(C 6 H 12 O 2 )] were mixed for single coctail source. Among the various deposition parameters, control of the oxygen flow rate turned out to be crucial for determining the phase formation, resistivity, and the composition ratio of (Ba,Sr)RuO 3 films. Highly (110)-textured (Ba,Sr)RuO 3 film was obtained when Ar/O 2 ratio was 100/300sccm with the source flow rate of 0.075sccm. Oxygen annealin...

A microscopic model for the resistance drift in the phase-change memory is proposed based on the first-principles results on the compressed amorphous Ge2Sb2Te5. First, it is shown that the residual pressure in the phase-change memory cell can be significant due to the density change accompanying the phase transformation. Our previous first-principles calculations showed that the energy gap is reduced and the density of localized in-gap states increases as the cell is pressurized. This indicates that the compressed amorphous Ge2Sb2Te5 is more conducting than those made under stress-free conditions. In addition, the crystallization dynamics was also accelerated under compressive stress. Based on these theoretical results, we propose a mechanism for the resistance drift in which the relaxation process in the amorphous Ge2Sb2Te5 corresponds to the growth of the crystalline nuclei inside the amorphous matrix, thereby lowering the internal stress. Our model can consistently explain several experimental observations such as the dependence of the drift exponent on the amorphous size.

Electrical conduction mechanisms for Pt/(Ba0.5Sr0.5)TiO3 (BST)/Pt, IrO2/BST/IrO2, and Pt/BST/IrO2 capacitors were studied. The Pt/BST/Pt capacitor shows a Schottky emission behavior with interface potential barrier heights of about 1.5–1.6 eV. The barrier height is largely determined by the surface electron trap states of the BST. The IrO2/BST interface shows an ohmic contact nature due to the elimination of the surface trap states as the result of the formation of strong chemical bonds between the IrO2 and BST which results in the Poole–Frenkel emission conduction mechanism. Pt/BST/IrO2 capacitor shows Schottky emission behavior and a positive temperature coefficient of resistivity (PTCR) effect depending on the bias polarity. The electron trap states at the Pt/BST interface and the positive space charges within the carrier depletion layer result in the PTCR effect.

Variations of the leakage current behaviors and interface potential barrier height (φ B ) of rf-sputter deposited (Ba, Sr)TiO3 (BST) thin films, with thickness ranging from 20nm to 150 nm are investigated as a function of the thickness and bias voltages. The top and bottom electrodes are dc-sputter-deposited Pt films. φ B critically depends on the BST film deposition temperature, postannealing atmosphere and time after the annealing. The postannealing under N2 atmosphere results in a high interface potential barrier height and low leakage current. Maintaining the BST capacitor in air for a long time reduces the φ B from about 2.4 eV to 1.6eV due to the oxidation. φ B is not so dependent on the film thickness in this experimental range. The leakage conduction mechanism is very dependent on the BST film thickness; the 20nm thick film shows tunneling current, 30 and 40 nm thick films show Schottky emission current and the thicker films show a mixed characteristics and bulk and interface limited curr...

SrTiO3 thin films are deposited by a liquid source metal-organic chemical vapor deposition (MOCVD). The effects of oxidants on the deposition characteristics and dielectric properties of the films are mainly tested. O2, N2O and O2 + N2O gases are used as the oxidants and the films with Ti-rich and Sr-rich compositions are obtained when O2 and N2O is used, respectively. Deposition of thin initial layer under O2 atmosphere is very effective to obtain large dielectric constant of the SrTiO3 thin film when the main layer is deposited under O2 + N2O atmosphere. The dielectric constants of 40 nm thick SrTiO3 films with thin O2, N2O initial layers and without the initial layers are 235, 145 and 210, respectively.

Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2–3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.

We investigate the effects of pressure on atomic and electronic structures of amorphous ${\text{Ge}}_{2}{\text{Sb}}_{2}{\text{Te}}_{5}$ using first-principles methods. The supercell volume is varied from 0.94 to 1.13 times the nominal amorphous volume in melt-quench simulations. When the simulation cell is compressed, we find that the energy gap is reduced and the number of localized in-gap states is increased. These results indicate that pressurized amorphous ${\text{Ge}}_{2}{\text{Sb}}_{2}{\text{Te}}_{5}$ exhibits better conduction than ${\text{Ge}}_{2}{\text{Sb}}_{2}{\text{Te}}_{5}$ formed under stress-free conditions. We also find that the positive pressure increases the densities of fourfold rings in amorphous ${\text{Ge}}_{2}{\text{Sb}}_{2}{\text{Te}}_{5}$, shifting the local order toward the crystalline phase. Consistently, fast crystallization is identified for compressed amorphous ${\text{Ge}}_{2}{\text{Sb}}_{2}{\text{Te}}_{5}$.

We present a new-type confine structure within 7.5 nm width dash-contact for sub 20 nm generation PRAMs. Phase change material (PCM) by chemical vapor deposition (CVD) was perfectly filled in a 7.5 nm width dash-contact without void along with 30 nm depth. By adopting confined CVD-PCM, we were able to reduce the reset current below ~160 muA and to obtain high reliability. In addition, the programming time of dash-confined cell was much improved to 50 ns due to volume confinement of PCM cell. Consequently, we firstly demonstrate the high performance of the 7.5 nm width confined cell, which is the smallest size close to physical limit.

first present a PRAM with confinement of chemically vapor deposited GeSbTe (CVD GST) within high aspect ratio 50 nm contact for sub 50 nm generation PRAMs. By adopting confined GST, we were able to reduce the reset current below ~260 muA and thermally stable CVD Ge2Sb2Te5 compound having hexagonal phase was uniformly filled in a contact while maintaining constant composition along with 150 nm depth. Our results indicate that the confined cell structure of 50 nm contact is applicable to PRAM device below 50 nm design rule due to small GST size based on small contact and direct top electrode contact, reduced reset current, minimized etch damage, and low thermal disturbance effect.

The effects of plasma surface treatment, using N2O gas, of Ba0.5Sr0.5TiO3 (BST) film on the leakage current characteristic of a Pt/BST/Pt capacitor were investigated. As a result of exposure of BST film to the plasma, the leakage current density of the BST capacitor decreased by two orders of magnitude in the high voltage region, and higher onset voltage of an abrupt increase in leakage current was observed. The improvement of leakage properties of BST films can be attributed to the elimination of the bulged curve in the leakage current characteristics. Thermal desorption spectroscopy showed that the elimination was closely related to the reduction of carbon content in the BST film.

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

Highly manufacturable 64Mbit PRAM has been successfully fabricated using N-doped Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) and optimal GST etching process. Using those technologies, it was possible to achieve the low writing current of 0.6 mA and clear separation between SET and RESET resistance distributions. The 64Mb PRAM was designed to support commercial NOR flash memory compatible interfaces. Therefore, the fabricated chip was tested under the mobile application platform and its functionality and reliability has been evaluated by operation temperature dependency, disturbance, endurance, and retention. Finally, it was clearly demonstrated that high density PRAM can be fabricated in the product level with strong reliability to produce new nonvolatile memory markets.

Phase change RAM (PRAM) is a promising memory that can solve the problems of conventional memory - scalability, write/read speed and reliability. The process technologies for the integration of high density PRAM are reviewed. The most important challenge of PRAM is the reduction of writing current. Various approaches to reduce the writing current are reviewed and other key factors for the high density PRAM are discussed.

We have integrated a phase-change chalcogenide random access memory, completely based on 0.24 /spl mu/m-CMOS technologies. A twin cell and BL clamping circuits are introduced to enlarge fabrication tolerance and to reduce cell perturbation during reading operation. To draw back current as much as possible, Co salicidation is also applied to transistor formation. By constructing a simple cell structure with Ge/sub 2/Sb/sub 2/Te/sub 5/, we have observed reliable phase-transitions by driving current through MOS transistors. With 100 ns-writing pulses of 2 mA for RESET and 0.6 mA for SET, the device operates successfully with a considerable sensing signal at reading voltage of as low as 0.2 V.

By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density phase-change random access memory. We have investigated the phase transition behaviors as a function of various process factors including contact size, cell size and thickness, doping concentration in chalcogenide material and cell structure. As a result, we have observed that the writing current is reduced down to 0.7 mA.

We have developed a novel cell structure of PRAM with metal interlayer. This novel structure has been proposed to solve the over-programming fail. We have examined the cause of over-programming by simulation of the phase transition of chalcogenide and successfully demonstrated reliable cell operation of this novel structure in writing current level, crystallization speed, and endurance. It can be explained by a model in which the metal interlayer is a local heat sink and the top GST layer is a thermal insulator.

We have fully integrated a nonvolatile random access memory by successfully incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. As well as basic characteristics of the memory operation, we have also observed reliable performances of the device on hot temperature operation, endurance against repetitive phase transition, writing imprint, reading disturbance and data retention.

The Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access Memory). Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.

We first developed a novel self-aligned electroplating process to fabricate Pt electrodes for integrated high-dielectric capacitors. Electroplated Pt filled 120 nm-wide buried contact (BC) holes (aspect ratio 2:1). Pt pillars of 210 nm diameter and 650 nm height were successfully fabricated. The leakage current density of sputtered BST capacitors using electroplated bottom Pt was less than 200 nA/cm/sup 2/ at /spl plusmn/1.5 V. The oxide-equivalent thickness T/sub oxeq/ and dissipation factor of 40 nm-thick BST films were 0.70 nm and 0.0080 at 0 V, respectively.

A new two-step post-annealing process to prevent degradation of integrated BST capacitors was developed. By this process, the increment of capacitance and the reduction of leakage current were obtained without barrier oxidation. A concave-type capacitor structure with buried barrier using Pt electrodes and MOCVD BST films was demonstrated in order to solve the integration problems such as Pt etching and the contact between the BST and the barrier. The electrical properties of MOCVD BST capacitor in 3-dimensional structure were investigated.

An integrated BST capacitor with Pt electrodes and TiSiN diffusion barrier, covered by SiO/sub 2/ spacers, is fabricated. Excellent diffusion barrier and oxidation resistant properties of TiSiN, further protected from being oxidized by the SiO/sub 2/ spacer, make post annealing up to 650/spl deg/C possible. The 0.3/spl times/0.8 /spl mu/m/sup 2/ sized capacitor having 0.2 /spl mu/m height with 256 M density shows 72 fF/cell of capacitance and 1.0 fA/cell@+1.0 V of leakage current density after the post annealing at 650/spl deg/C. The capacitance corresponds to a value of 25 fF/cell of a DRAM with 0.30 /spl mu/m-pitch, which is expected to be the cell size of 1 giga-bit density DRAM.

Liquid and amorphous structures of Ge2Sb2Te5 are theoretically studied with various exchange-correlation functionals. It is found that the balance of competing local orders around Ge atoms is substantially affected by the functional type, and the hybrid functional leads to structures that are in best agreement with experiment. The delocalization error inherent in semilocal functionals results in over-population of octahedral Ge configurations, which is compounded by the limitation of melt-quench processes in identifying the most stable amorphous structure. The present work underscores the importance of functional choice when competing local orders present in disordered systems.

To investigate an amorphous structure of Ge(2)Sb(2)Te(5) that satisfies the 8-N rule (so-called 'ideal glass'), we perform alternative melt-quench simulations on Si(2)As(2)Se(5) and replace atoms in the final structure with Ge-Sb-Te. The resulting structures have salient features of the 8-N rule such as the tetrahedral configuration for all Ge atoms and the localized Te lone pairs at the valence top. In addition, the average Ge-Te and Sb-Te distances are in good agreement with experiment. The energetic stability of the ideal glass supports the existence of this amorphous structure that is distinct from the melt-quenched glass. From the analysis of electronic structures and optical dielectric constants, it is concluded that the electronic character of the melt-quenched amorphous Ge(2)Sb(2)Te(5) lies in between the resonant p-bonding of the crystalline phase and the covalent bonding of the ideal glass.

It has been demonstrated that the crystallization behaviors of undoped and N-doped Ge2Sb2Te5 (GST) films can be evaluated by studying the thermomechanical behavior of the films. The crystallization temperatures (Tc) for undoped and 15 at. % N-doped GST films were determined to be about 150 and 250 °C, respectively. The activation energies for crystallization (Ea) were calculated to be 2.30, 3.29, and 3.72 eV for undoped, 10 at. % N-doped, and 15 at. % N-doped GST, respectively, by the Kissinger plot. For 15 at. % N-doped film, both the glass transition temperature (Tg) and Tc were determined to be about 150 °C, as determined by the thermomechanical characteristics.

Variations of the leakage current behaviors and interface potential barrier height (ΦB) of rf-sputter deposited (Ba, Sr)TiO3 (BST) thin films with thicknesses ranging from 20 nm to 150 nm are investigated as a function of the thickness and bias voltages. The top and bottom electrodes are dc-sputter-deposited Pt films. ΦB critically depends on the BST film deposition temperature, postannealing atmosphere and time after the annealing. The postannealing under N2 atmosphere results in a high interface potential barrier height and low leakage current. Maintaining the BST capacitor in air for a long time reduces the ΦB from about 2.4 eV to 1.6 eV due to the oxidation. ΦB is not so dependent on the film thickness in this experimental range. The leakage conduction mechanism is very dependent on the BST film thickness; the 20 nm thick film shows tunneling current, 30 and 40 nm thick films show Schottky emission current.

The deposition characteristics of (Ba, Sr)TiO3 (BST) thin films using a liquid source metal-organic chemical vapor deposition on a 6-inch-diameter Pt/SiO2/Si wafer were investigated. Ba(DPM)2 tetraglyme, Sr(DPM)2 tetraglyme and Ti(DPM)2(O-i-Pr)2, dissolved in n-butyl acetate, were used as the sources of Ba, Sr and Ti, respectively. Step coverage, within-wafer uniformities in composition and thickness of the BST films were investigated as a function of substrate temperatures ranging from 420° C to 570° C. As the substrate temperature decreased, the step coverage improved, whereas the within-wafer uniformities degraded. From BST films deposited in a temperature range from 450° C to 480° C, good step coverage (>80%), as well as good within-wafer uniformity were obtained. However, in that temperature range, hazy deposition was observed due to many humps on the surface. The humps are an agglomeration of crystalline grains and are a few hundred Å in diameter, which have a Ti-rich composition compared to flat film region.

Electrical conduction behaviors of Pt/ (Ba, Sr)TiO3/Pt thin film capacitors having top Pt electrodes with different deposition powers are investigated. The capacitors having top Pt electrode with deposition power of 0.2 kW show Schottky emission behavior at both top and bottom electrode interfaces with potential barrier heights of 1.24–1.48 eV and 1.88–2.08 eV, respectively. However, the capacitor having top Pt electrode with larger deposition power of 0.5 kW shows Schottky emission behavior only at bottom electrode interface with barrier of 1.61–1.89 eV. Interface with top electrode appears to have very low resistance, and a positive temperature coefficient of resistivity (PTCR) effect is observed when the electrons are injected from the top electrode to bottom electrode through BST film. Top Pt electrode becomes very rough by grain growth during postannealing when the top Pt is deposited with powers of larger than 0.5 kW. Roughening of the top Pt results in the low-resistance contact behavior at the interface between top Pt and BST, which results in PTCR effect.

High-dielectric Ba0.5Sr0.5TiO3 (BST) thin films are grown on Ir and IrO2 electrodes by a rf sputtering method. The structural and electrical properties of BST films are investigated. After postannealing at 750° C for 30 min in N2 atmosphere, the interface between BST and IrO2 remains flat and the IrO2 does not show any structural change. On the other hand, a thin IrO2 layer is formed at the interface between the BST and Ir after the same post-annealing. A larger grain size of BST film is obtained on the Ir electrode compared to that of BST film on the IrO2 electrode. Dielectric constants of 36-nm-thick BST films on Ir and IrO2 are 338 and 290, respectively. The leakage current densities of both the Pt/BST/Ir and Pt/BST/IrO2 capacitors are about 20 nA/cm2 at ±1.5 V, which is sufficiently small for application to dynamic random access memory devices.

Iridium oxide ( IrO2) thin films were successfully grown by a DC magnetron reactive sputtering method. It was found that the crystalline nature and morphology of IrO2 films were strongly dependent on the oxygen partial pressure, total pressure and growth temperature. The growth of IrO2 is well explained by the generic curve for the total pressure as a function of O2 content. The films showed good barrier performance between Pt and poly-Si up to 750° C. A 40-nm-thick Ba0.5Sr0.5TiO3 film was grown by RF magnetron sputtering on the Pt/IrO2/poly-Si electrode. The leakage current density and dielectric constant of a Pt/Ba0.5Sr0.5TiO3/Pt capacitor on the IrO2/poly-Si electrode were comparable to those of the capacitor on a SiO2/Si substrate. However, an additional ohmic layer was required to prevent the formation of a SiO2 layer between the IrO2 and poly-Si.

SrTiO3 thin films with thicknesses ranging from 30 nm to 60 nm were grown on 6-inch-diameter, platinized Si wafers by liquid source metal-organic chemical vapor deposition (MOCVD). The crystalline quality and cation concentrations of the films are strongly dependent on the deposition temperature with optimum temperatures ranging from 500° C to 550° C. Semi-conformal deposition on submicron-sized storage node patterns is obtained but further improvements in conformality and reproducibility are required. The dielectric constant is about 210 irrespective of the film thickness and leakage current densities are sufficiently small for the dynamic random access memory (DRAM) applications. SiO2 equivalent thickness (T ox) of the 30-nm-thick STO film is 0.51 nm. The finding that the leakage current density and dielectric constant are independent of the film thickness can be explained by a fully depleted model of the STO film.

Tacticity dependence of thermal stability of poly(methyl methacrylate)s was examined under nitrogen by differential scanning calorimetric analysis using the isotactic PMMAs prepared with t-C4H9MgBr and syndiotactic PMMAs prepared with t-C4H9Li-(C2H5)3Al (Al/Li=3), which had the same chemical structure from α-end to ω-end and similar molecular weights. As the molecular weight became smaller, the degradation temperatures of both the isotactic and syndiotactic PMMAs became higher. The syndiotactic PMMAs showed higher degradation temperatures than the isotactic ones with similar molecular weights.