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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Abstract Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied. Several strategies were proposed for the epitaxy such as hydrogen purging to deplete the access of P atoms on Si surface, and/or inserting a Si or Si0.93Ge0.07 spacers on both sides of P-doped Si layers, and substituting SiH4 by SiH2Cl2 (DCS). Experimental results showed that the segregation and auto-doping could also be relieved by adding 7% Ge to P-doped Si. The structure had good lattice quality and almost had no strain relaxation. The selective etching between P-doped Si (or P-doped Si0.93Ge0.07) and SiGe was also discussed by using wet and dry etching. The performance and selectivity of different etching methods were also compared. This paper provides knowledge of how to deal with the challenges or difficulties of epitaxy and etching of n-type layers in vertical GAAFETs structure.

Among photodetectors, avalanche photodiodes (APDs) have an important place due to their excellent sensitivity to light. APDs transform photons into electrons and then multiply the electrons, leading to an amplified photocurrent. APDs are promising for faint light detection owing to this outstanding advantage, which will boost LiDAR applications. Although Si APDs have already been commercialized, their spectral region is very limited in many applications. Therefore, it is urgently demanded that the spectral region APDs be extended to the short-wavelength infrared (SWIR) region, which means better atmospheric transmission, a lower solar radiation background, a higher laser eye safety threshold, etc. Up until now, both Ge (GeSn) and InGaAs were employed as the SWIR absorbers. The aim of this review article is to provide a full understanding of Ge(GeSn) and InGaAs for PDs, with a focus on APD operation in the SWIR spectral region, which can be integrated onto the Si platform and is potentially compatible with CMOS technology.

The development of the low dislocation density of the Si-based GaAs buffer is considered the key technical route for realizing InAs/GaAs quantum dot lasers for photonic integrated circuits. To prepare the high-quality GaAs layer on the Si substrate, we employed an engineered Ge-buffer on Si, used thermal cycle annealing, and introduced filtering layers, e.g., strained-layer superlattices, to control/reduce the threading dislocation density in the active part of the laser. In this way, a low defect density of 2.9 × 107 cm−2 could be achieved in the GaAs layer with a surface roughness of 1.01 nm. Transmission electron microscopy has been applied to study the effect of cycling, annealing, and filtering layers for blocking or bending threading-dislocation into the InAs QDs active region of the laser. In addition, the dependence of optical properties of InAs QDs on the growth temperature was also investigated. The results show that a density of 3.4 × 1010 InAs quantum dots could be grown at 450 °C, and the photoluminescence exhibits emission wavelengths of 1274 nm with a fullwidth at half-maximum (FWHM) equal to 32 nm at room temperature. The laser structure demonstrates a peak at 1.27 μm with an FWHM equal to 2.6 nm under a continuous-wave operation with a threshold current density of ∼158 A/cm2 for a 4-μm narrow-ridge width InAs QD device. This work, therefore, paves the path for a monolithic solution for photonic integrated circuits when III−V light sources (which is required for Si photonics) are grown on a Ge-platform (engineered Ge-buffer on Si) for the integration of the CMOS part with other photonic devices on the same chip in near future.

The realization of high-performance Si-based III-V quantum-dot (QD) lasers has long attracted extensive interest in optoelectronic circuits. This manuscript presents InAs/GaAs QD lasers integrated on an advanced GaAs virtual substrate. The GaAs layer was originally grown on Ge as another virtual substrate on Si wafer. No patterned substrate or sophisticated superlattice defect-filtering layer was involved. Thanks to the improved quality of the comprehensively modified GaAs crystal with low defect density, the room temperature emission wavelength of this laser was allocated at 1320 nm, with a threshold current density of 24.4 A/cm−2 per layer and a maximum single-facet output power reaching 153 mW at 10 °C. The maximum operation temperature reaches 80 °C. This work provides a feasible and promising proposal for the integration of an efficient O-band laser with a standard Si platform in the near future.

As the scaling technology in the silicon-based semiconductor industry is approaching physical limits, it is necessary to search for proper materials to be utilized as alternatives for nanoscale devices and technologies. On the other hand, carbon-related nanomaterials have attracted so much attention from a vast variety of research and industry groups due to the outstanding electrical, optical, mechanical and thermal characteristics. Such materials have been used in a variety of devices in microelectronics. In particular, graphene and carbon nanotubes are extraordinarily favorable substances in the literature. Hence, investigation of carbon-related nanomaterials and nanostructures in different ranges of applications in science, technology and engineering is mandatory. This paper reviews the basics, advantages, drawbacks and investigates the recent progress and advances of such materials in micro and nanoelectronics, optoelectronics and biotechnology.

In recent years, nanodevices have attracted a large amount of attention due to their low power consumption and fast operation in electronics and photonics, as well as their high sensitivity in sensor applications [...]

In our environment, the large availability of wasted heat has motivated the search for methods to harvest heat. As a reliable way to supply energy, SiGe has been used for thermoelectric generators (TEGs) in space missions for decades. Recently, micro-thermoelectric generators (μTEG) have been shown to be a promising way to supply energy for the Internet of Things (IoT) by using daily waste heat. Combining the predominant CMOS compatibility with high electric conductivity and low thermal conductivity performance, Si nanowire and SiGe nanowire have been a candidate for μTEG. This review gives a comprehensive introduction of the Si, SiGe nanowires, and their possibility for μTEG. The basic thermoelectric principles, materials, structures, fabrication, measurements, and applications are discussed in depth.

In this manuscript, a novel dual-step selective epitaxy growth (SEG) of Ge was proposed to significantly decrease the defect density and to create fully strained relaxed Ge on a Si substrate. With the single-step SEG of Ge, the threading defect density (TDD) was successfully decreased from 2.9 × 107 cm−2 in a globally grown Ge layer to 3.2 × 105 cm−2 for a single-step SEG and to 2.84 × 105 cm−2 for the dual-step SEG of the Ge layer. This means that by introducing a single SEG step, the defect density could be reduced by two orders of magnitude, but this reduction could be further decreased by only 11.3% by introducing the second SEG step. The final root mean square (RMS) of the surface roughness was 0.64 nm. The strain has also been modulated along the cross-section of the sample. Tensile strain appears in the first global Ge layer, compressive strain in the single-step Ge layer and fully strain relaxation in the dual-step Ge layer. The material characterization was locally performed at different points by high resolution transmission electron microscopy, while it was globally performed by high resolution X-ray diffraction and photoluminescence.

In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive strain. Two etching methods, the wet etching and in situ HCl dry etching methods, were studied to achieve a better etching topography. In addition, the selective epitaxial growth of Ge material was performed on a patterned substrate using reduced pressure chemical vapor deposition. The results show that a V-shaped structure formed at the bottom of the dummy Si-fins using the wet etching method, which is beneficial to the suppression of dislocations. In addition, compressive strain was introduced to the Ge channel after the Ge selective epitaxial growth, which benefits the pMOS transport characteristics. The pattern dependency of the Ge growth over the patterned wafer was measured, and the solutions for uniform epitaxy are discussed.

GeSn materials have attracted considerable attention for their tunable band structures and high carrier mobilities, which serve well for future photonic and electronic applications. This research presents a novel method to incorporate Sn content as high as 18% into GeSn layers grown at 285–320 °C by using SnCl4 and GeH4 precursors. A series of characterizations were performed to study the material quality, strain, surface roughness, and optical properties of GeSn layers. The Sn content could be calculated using lattice mismatch parameters provided by X-ray analysis. The strain in GeSn layers was modulated from fully strained to partially strained by etching Ge buffer into Ge/GeSn heterostructures . In this study, two categories of samples were prepared when the Ge buffer was either laterally etched onto Si wafers, or vertically etched Ge/GeSnOI wafers which bonded to the oxide. In the latter case, the Ge buffer was initially etched step-by-step for the strain relaxation study. Meanwhile, the Ge/GeSn heterostructure in the first group of samples was patterned into the form of micro-disks. The Ge buffer was selectively etched by using a CF4/O2 gas mixture using a plasma etch tool. Fully or partially relaxed GeSn micro-disks showed photoluminescence (PL) at room temperature. PL results showed that red-shift was clearly observed from the GeSn micro-disk structure, indicating that the compressive strain in the as-grown GeSn material was partially released. Our results pave the path for the growth of high quality GeSn layers with high Sn content, in addition to methods for modulating the strain for lasing and detection of short-wavelength infrared at room temperature.

Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized.

GeSn alloys have already attracted extensive attention due to their excellent properties and wide-ranging electronic and optoelectronic applications. Both theoretical and experimental results have shown that direct bandgap GeSn alloys are preferable for Si-based, high-efficiency light source applications. For the abovementioned purposes, molecular beam epitaxy (MBE), physical vapour deposition (PVD), and chemical vapor deposition (CVD) technologies have been extensively explored to grow high-quality GeSn alloys. However, CVD is the dominant growth method in the industry, and it is therefore more easily transferred. This review is focused on the recent progress in GeSn CVD growth (including ion implantation, in situ doping technology, and ohmic contacts), GeSn detectors, GeSn lasers, and GeSn transistors. These review results will provide huge advancements for the research and development of high-performance electronic and optoelectronic devices.

Abstract In this paper, pMOSFETs featuring atomic layer deposition (ALD) tungsten (W) using SiH4 and B2H6 precursors in 22 nm node CMOS technology were investigated. It is found that, in terms of threshold voltage, driving capability, carrier mobility, and the control of short-channel effects, the performance of devices featuring ALD W using SiH4 is superior to that of devices featuring ALD W using B2H6. This disparity in device performance results from different metal gate-induced strain from ALD W using SiH4 and B2H6 precursors, i.e. tensile stresses for SiH4 (~2.4 GPa) and for B2H6 (~0.9 GPa).

Gate-all-around (GAA) field-effect transistors have been proposed as one of the most important developments for CMOS logic devices at the 3 nm technology node and beyond. Isotropic etching of silicon–germanium (SiGe) for the definition of nano-scale channels in vertical GAA CMOS and tunneling FETs has attracted more and more attention. In this work, the effect of doping on the digital etching of Si-selective SiGe with alternative nitric acids (HNO3) and buffered oxide etching (BOE) was investigated in detail. It was found that the HNO3 digital etching of SiGe was selective to n+-Si, p+-Si, and intrinsic Si. Extensive studies were performed. It turned out that the selectivity of SiGe/Si was dependent on the doped types of silicon and the HNO3 concentration. As a result, at 31.5% HNO3 concentration, the relative etched amount per cycle (REPC) and the etching selectivity of Si0.72Ge0.28 for n+-Si was identical to that for p+-Si. This is particularly important for applications of vertical GAA CMOS and tunneling FETs, which have to expose both the n+ and p+ sources/drains at the same time. In addition, the values of the REPC and selectivity were obtained. A controllable etching rate and atomically smooth surface could be achieved, which enhanced carrier mobility.

For the formation of nano-scale Ge channels in vertical Gate-all-around field-effect transistors (vGAAFETs), the selective isotropic etching of Ge selective to Ge0.8Si0.2 was considered. In this work, a dual-selective atomic layer etching (ALE), including Ge0.8Si0.2-selective etching of Ge and crystal-orientation selectivity of Ge oxidation, has been developed to control the etch rate and the size of the Ge nanowires. The ALE of Ge in p+-Ge0.8Si0.2/Ge stacks with 70% HNO3 as oxidizer and deionized (DI) water as oxide-removal was investigated in detail. The saturated relative etched amount per cycle (REPC) and selectivity at different HNO3 temperatures between Ge and p+-Ge0.8Si0.2 were obtained. In p+-Ge0.8Si0.2/Ge stacks with (110) sidewalls, the REPC of Ge was 3.1 nm and the saturated etching selectivity was 6.5 at HNO3 temperature of 20 °C. The etch rate and the selectivity were affected by HNO3 temperatures. As the HNO3 temperature decreased to 10 °C, the REPC of Ge was decreased to 2 nm and the selectivity remained at about 7.4. Finally, the application of ALE in the formation of Ge nanowires in vGAAFETs was demonstrated where the preliminary Id–Vds output characteristic curves of Ge vGAAFET were provided.

This article presents a novel method to grow a high-quality compressive-strain Ge epilayer on Si using the selective epitaxial growth (SEG) applying the RPCVD technique. The procedures are composed of a global growth of Ge layer on Si followed by a planarization using CMP as initial process steps. The growth parameters of the Ge layer were carefully optimized and after cycle-annealing treatments, the threading dislocation density (TDD) was reduced to 3 × 107 cm−2. As a result of this process, a tensile strain of 0.25% was induced, whereas the RMS value was as low as 0.81 nm. Later, these substrates were covered by an oxide layer and patterned to create trenches for selective epitaxy growth (SEG) of the Ge layer. In these structures, a type of compressive strain was formed in the SEG Ge top layer. The strain amount was −0.34%; meanwhile, the TDD and RMS surface roughness were 2 × 106 cm−2 and 0.68 nm, respectively. HRXRD and TEM results also verified the existence of compressive strain in selectively grown Ge layer. In contrast to the tensile strained Ge layer (globally grown), enhanced PL intensity by a factor of more than 2 is partially due to the improved material quality. The significantly high PL intensity is attributed to the improved crystalline quality of the selectively grown Ge layer. The change in direct bandgap energy of PL was observed, owing to the compressive strain introduced. Hall measurement shows that a selectively grown Ge layer possesses room temperature hole mobility up to 375 cm2/Vs, which is approximately 3 times larger than that of the Ge (132 cm2/Vs). Our work offers fundamental guidance for the growth of high-quality and compressive strain Ge epilayer on Si for future Ge-based optoelectronics integration applications.

This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy; the start point of the experiments includes Stranski–Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides. Afterwards, a two-dimensional Ge layer is formed from the coalescing of the nuclides. The evolution of the strain from the beginning stage of the growth up to the full Ge layer has been investigated. Material characterization results show that Ge epilayer with 400 nm LT-Ge buffer layer features at least the root mean square (RMS) value and it’s threading dislocation density (TDD) decreases by a factor of 2. In view of the 400 nm LT-Ge buffer layer, the 1000 nm Ge epilayer with HT-Ge growth temperature of 650 °C showed the best material quality, which is conducive to the merging of the crystals into a connected structure eventually forming a continuous and two-dimensional film. After increasing the thickness of Ge layer from 900 nm to 2000 nm, Ge surface roughness decreased first and then increased slowly (the RMS value for 1400 nm Ge layer was 0.81 nm). Finally, a high-temperature annealing process was carried out and high-quality Ge layer was obtained (TDD=2.78 × 107 cm−2). In addition, room temperature strong photoluminescence (PL) peak intensity and narrow full width at half maximum (11 meV) spectra further confirm the high crystalline quality of the Ge layer manufactured by this optimized process. This work highlights the inducing, increasing, and relaxing of the strain in the Ge buffer and the signature of the defect formation.

In this article, we demonstrated novel methods to improve the performance of p-i-n photodetectors (PDs) on a germanium-on-insulator (GOI). For GOI photodetectors with a mesa diameter of 10 μm, the dark current at −1 V is 2.5 nA, which is 2.6-fold lower than that of the Ge PD processed on Si substrates. This improvement in dark current is due to the careful removal of the defected Ge layer, which is formed with the initial growth of Ge on Si. The bulk leakage current density and surface leakage density of the GOI detector at −1 V are as low as 1.79 mA/cm2 and 0.34 μA/cm, respectively. GOI photodetectors with responsivity of 0.5 and 0.9 A/W at 1550 and 1310 nm wavelength are demonstrated. The optical performance of the GOI photodetector could be remarkably improved by integrating a tetraethylorthosilicate (TEOS) layer on the oxide side due to the better optical confinement and resonant cavity effect. These PDs with high performances and full compatibility with Si CMOS processes are attractive for applications in both telecommunications and monolithic optoelectronics integration on the same chip.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

The unique electronic properties of semiconductor nanowires, in particular silicon nanowires (SiNWs), are attractive for the label-free, real-time, and sensitive detection of various gases. Therefore, over the past two decades, extensive efforts have been made to study the gas sensing function of NWs. This review article presents the recent developments related to the applications of SiNWs for gas sensing. The content begins with the two basic synthesis approaches (top-down and bottom-up) whereby the advantages and disadvantages of each approach have been discussed. Afterwards, the basic sensing mechanism of SiNWs for both resistor and field effect transistor designs have been briefly described whereby the sensitivity and selectivity to gases after different functionalization methods have been further presented. In the final words, the challenges and future opportunities of SiNWs for gas sensing have been discussed.

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

The growth of high frequency HBT structures using silane-based epitaxy has been studied. The integrity of SiGe layers in the base and the control of the collector profile using As- or P-doping grown at 650 oC have been investigated. The results showed that the growth rate of SiGe layers has a strong effect on the evolution of defect density in the structure. Furthermore, B-doped SiGe layers have a~higher thermal stability compared to undoped layers. The analysis of the collector profiles showed a higher incorporation of P in silane-based epitaxy compared to As. Meanwhile, the growth of As- or P-doped layers on the patterned substrates suffered from a high loading effect demanding an accurate calibration.