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High cholesterol could be dangerous, along with the deposits of other substances, such as fat, on the walls of the arteries. These plaques can reduce blood flow through the arteries, which in turn can cause complications such as chest pain, blood clots, and heart attack. Hence, there is a need for an efficient way to measure the concentration of cholesterol in blood vessels with great accuracy to predict its risk on health. The present study aims to measure the concentration of cholesterol and track it accurately in the blood vessels using an ultrasound pressure sensor, which detects the concentration of cholesterol and produces a pressure field around its surface that is directly proportional to the concentration. This field can be tracked by ultrasound. In this study, the experiments conducted involved the insertion of aluminum nanoparticles, which represent a pressure sensor coated with a massless piezoelectric aluminum nitride nanoplate, into simulated blood vessels containing different concentrations that mimic human blood. The sensitivity of the blood vessels was monitored at different time periods. Moreover, an experimental setup was constructed to validate the possibility of using existing ultrasound medical imaging technologies in tracking the proposed nano biosensors. The setup involves prototyping a medical phantom with a specific acoustic characteristic for simulating human tissues. Various clinical scenarios have been imitated and the possibility of tracking these novel micro electromechanical pressure biosensors has been discussed.

Most current modern devices have micro dimensions. For engineers and manufacturers, it is now possible to manufacture completely remote devices in a modern way. To determine the critical points in measuring the dimensions for the manufacturing of devices, which is achieved in practice and at an appropriate cost, numerous studies have been conducted around the world. Researchers have attempted to develop a pragmatic approach to interface various nanoscale devices together and to study their focal points and disadvantages. The objective of this study is to focus on modern trends in the manufacturing of nanoscale devices. These trends are divided into the following five sections: development of tribotronic devices, nanodevice fabrication using two-dimensional materials, fabrication using carbon nanotubes (CNTs), on-chip nanodevice fabrication, and nanodevices based on photonics. In this study, the views on these trends and how to effectively apply them in the future are presented. To enhance the structure and features of nanowires inside a scanning tunneling microscope (STM) scanner, a novel view about the structure of nanowire is presented. These nanowires demonstrate unique metal properties that enable them to operate in multiple environments with high efficiency. Using these nanowires inside an STM scanner can improve their ability to withstand high pressure because their metal properties minimize the chances of breakage.

This paper presents novel hardware of a unified architecture to compute the 4 × 4, 8 × 8, 16 × 16 and 32 × 32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications.

This paper presents an efficient implementation of the High Efficiency Video Coding (HEVC) decoder using Hardware/Software (HW/SW) co-design approach on the Zynq System on Chip (SoC) Platform. The reference software decoder HM 10.0 has been implemented under embedded Linux Operating System (OS). For real-time decoding, we provide hardware acceleration for the most computationally intensive parts of the HEVC decoder, which are the interpolation filters. The proposed design improves the processing throughput targeting on the resolution of 3840 × 2160 at a frame rate of 60 fps. HW/SW validation is achieved and examined in terms of resource utilization, throughput and power consumption. In order to improve the total decoding time, we propose to enable the Direct Memory Access (DMA) mode that can help speed page access and minimize the transfer time between the processor and hardware accelerators.

A constitutive model is developed that incorporates the wavy elastic response of an arc-shaped metallic glass (MG) ribbon subjected to applied progressive normal load. This model is based on the ev...

Arrhythmia is a dangerous disease in which the heart rhythm varies and it may be very fast or very slow. Rapid heartbeats can lead to shortness of breath, chest pain, and sudden weakness, whereas slow heartbeats can lead to dizziness, problems with concentration, and constant stress. Finding an effective treatment for arrhythmia has become a very important endeavor for researchers and clinicians. In this article, we review the latest methodologies used in arrhythmia diagnosis and treatment. They include the application of five different types of artificial neural networks trained by machine learning and powered by artificial intelligence: convolutional, recurrent, feedforward, radial basis function, and modular neural network. Some of these methodologies are merged to enhance accuracy and efficacy. This review suggests that more research needs to be carried out in merging neural network types for their application in electrocardiogram (ECG).

Methods for testing the presence of a virus in the blood are of interest to researchers and doctors because they determine how rapidly a virus is detected. In general, virus detection is a major scientific problem due to the serious effects of viruses on the human body. At present, only one virus can be detected in a single test. This potentially costs the medical establishment more time and money that could be saved if blood testing was more efficient. This study presents a qualitative method to enable doctors and researchers to detect more than one virus simultaneously. This was performed using quartz nanoparticles. Using polymer thin films of polydimethylsiloxane (PDMS), each chip emits a different frequency for each specific type of virus on the chip. The multiplicity of these chips allows for the detection of a number of viruses with the same number of nanoscale chips simultaneously. Blood flow around quartz nanoparticles was modelled. In this model, several conventional Quartz Crystal Microbalance (QCM) with nanostructures (Nano-QCM) particles are inserted into the three main types of blood vessels. The results showed that the best location for the Nano-QCM is the large artery and that it is possible to test for a number of viruses in all types of blood vessels.

In this paper, we propose an indoor visible light communication (VLC) system which makes use of Walsh precoding and multiple light-emitting diodes (LEDs) at the transmitter for multiplexing the data. The proposed VLC system is based on intensity modulation and uses the notion of spatial modulation for communicating the positive and negative values of the synthesized transmit signal using signal processing technique at the transmitter. We also illustrate the flexibility, ability, and easiness of the system to configure well in a multiuser environment. We have also developed a near-maximum likelihood (ML) detection technique for efficiently decoding the data bits at the receiver. The proposed near-ML reduces the search space involved in ML technique by using the initial ZF solution. The results of the simulation studies illustrate that the proposed technique offers a higher data rate and good bit error rate (BER) performance in indoor VLC environments.

High efficiency video coding (HEVC) is the latest video coding standard aimed to replace the H.264/AVC standard according to its high coding performance, which allows it to be mostly suitable for application in high definition videos. However, this performance is accompanied by a high computational complexity due principally to the motion estimation (ME) algorithm. As in H.264/AVC, the ME in HEVC is a highly computational demanding part that takes the largest part of the whole encoding time. Hence, many fast algorithms have been proposed in order to reduce computation, but, the majority, do not study how they can be effectively implemented by hardware. In this paper, two hardware architectures of the diamond pattern search algorithm for HEVC video coding with sequential and parallel techniques, are proposed. These architectures are based on parallel processing techniques. The sequential and parallel VHDL codes have been verified and can achieve at a high frequency on a Virtex-7 field-programmable gate-array design (FPGA) circuit. Compared to other designs, our parallel design provides better efficient implementation of available resources on FPGA. Our architecture can meet the real-time processing of the FHD @ 30 frames per second.

Compound nanoparticle drug delivery system plays an important role in the interaction with lymph nodes. There are three primary types of lymphocytes: B cells, T cells, and natural killer cells. When the cells of the immune system turn carcinogenic, they assault body cells. The lymph fluid plays an important role in attacking healthy cells of the body; hence, this paper aimed to design a drug delivery system, which can efficiently direct nanoparticles to target the infected cells, helping in high-speed elimination of such cells. The proposed design depends on the interaction between these molecules, and the intelligent nano-controller has the ability to guide the nanoparticles by anaerobic contact. The proposed design proved that the smaller the nanoparticle size and density, the less dynamic viscosity of the liquid would be, which would reflect its resistance to flow. In addition, it was concluded that hydrogen molecules play a significant role in reducing lymphatic fluid resistance due to their low density.

The HEVC video coding standard supports different transform sizes ranging from 4-point to 32-point. In fact, multiple transform sizes improve coding efficiency, but increase as well the computational complexity. Hardware decoders apply different techniques to satisfy real-time requirements. This paper describes a novel design methodology of a unified 2D inverse core transform IICT. The hardware architecture is based on a 1D-IICT block and a transpose buffer FIFO memory used to store the intermediate values of 1D transform. All this process is controlled in such a way to reduce the hardware and memory resources. To support the different transform sizes, matrix multiplications are simplified based on transform blocks decomposition into fixed-size sub-blocks in previous works. The architecture was developed for an FPGA device. Synthesis results on Startix III FPGA device show that the proposed design, operating at 266 MHz, is sufficient to decode high resolution videos using only 10% of total pins and about 33% of the hardware resources offered.

The deblocking filter (DBF) constitutes an important part of the High Efficiency Video Coding (HEVC) standard. In this paper, a novel hardware architecture of the HEVC DBF is proposed for all block boundaries within a luma $32 \times 32$ coding block (CB) to reduce visual artifacts. The proposed hardware architecture employs a high degree of parallelism and includes pipeline structure in order to improve the throughput. Experimental results demonstrate that the proposed DBF architecture can reach a high operating clock frequency of 250 MHz and can support $3840\times 2160@50fps$ real-time applications on the Zynq system-on-chip (SoC).

This paper describes efficient hardware architecture for the deblocking filter used in H.264/AVC baseline profile video coding standard. The deblocking filter is a computationally and data intensive tool leading to an increased execution time of both encoding and decoding processes. In fact, we propose a novel edge filter ordering which needs 64 clock cycles to filter a Macroblock (MB). A specified memory organization is also applied in order to avoid unnecessarily waiting for availability of the pixels that will be filtered. The proposed architecture includes both pipelining and parallel processing techniques and is implemented in synthesizable HDL. This hardware is designed to be used as module of a complete H.264/AVC decoder which the functionality was validated on Nios II at 100 MHz.

Intravenous delivery is the fastest conventional method of delivering drugs to their targets in seconds, whereas intramuscular and subcutaneous injections provide a slower continuous delivery of drugs. In recent years, nanoparticle-based drug-delivery systems have gained considerable attention. During the progression of nanoparticles into the blood, the sound waves generated by the particles create acoustic pressure that affects the movement of nanoparticles. To overcome this issue, the impact of sound pressure levels on the development of nanoparticles was studied herein. In addition, a composite nanostructure was developed using different types of nanoscale substances to overcome the effect of sound pressure levels in the drug-delivery process. The results demonstrate the efficacy of the proposed nanostructure based on a group of different nanoparticles. This study suggests five materials, namely, polyimide, acrylic plastic, Aluminum 3003-H18, Magnesium AZ31B, and polysilicon for the design of the proposed structure. The best results were obtained in the case of the movement of these molecules at lower frequencies. The performance of acrylic plastic is better than other materials, the sound pressure levels reached minimum values at frequencies of 1, 10, 20, and 60 nHz. Furthermore, an experimental setup was designed to validate the proposed idea using advanced biomedical imaging technologies. The experimental results demonstrate the possibilities of detecting, tracking, and evaluating the movement behaviors of nanoparticles. The experimental results also demonstrate that the lowest sound pressure levels were observed at lower frequency levels, thus proving the validity of the proposed computational model assumptions. The outcome of this study will pave the way to understand the interaction behaviors of nanoparticles with the surrounding biological environments, including the sound pressure effect, which could lead to the useof such an effect in facilitating directional and tactic movements of the micro- and nano-motors.

In this paper, we perform an implementation of the High Efficiency Video Coding (HEVC) decoder on ARM processor. The complexity of HM10.0 reference software decoder has been profiled, using GNU gprof under the embedded Linux. In order to give indication of the most complex modules, numerous sequences were tested, for different resolutions and with two different Quantization Parameter (QP) values. This paper reveals the bottlenecks of HM decoder and provides implementation guidelines for future real-time HEVC decoder.

High-efficiency video coding is the latest standardization effort of the International Organization for Standardization and the International Telecommunication Union. This new standard adopts an exhaustive algorithm of decision based on a recursive quad-tree structured coding unit, prediction unit, and transform unit. Consequently, an important coding efficiency may be achieved. However, a significant computational complexity is resulted. To speed up the encoding process, efficient algorithms based on fast mode decision and optimized motion estimation were adopted in this paper. The aim was to reduce the complexity of the motion estimation algorithm by modifying its search pattern. Then, it was combined with a new fast mode decision algorithm to further improve the coding efficiency. Experimental results show a significant speedup in terms of encoding time and bit-rate saving with tolerable quality degradation. In fact, the proposed algorithm permits a main reduction that can reach up to 75 % in encoding time. This improvement is accompanied with an average PSNR loss of 0.12 dB and a decrease by 0.5 % in terms of bit-rate.

This work proposes an FPGA architecture for the 1-D inverse transform of the latest video coding standard called the High Efficiency Video Coding standard (HEVC). This paper presents a new technique which computes the different sizes of the transform unit using a flexible architecture. Based on symmetrical characteristics of the elements in inverse transform matrices, the transform matrix is factorized into several matrices. This architecture supports all transform sizes i.e. 4×4, 8×8, 16×16, and 32×32. The synthesis results contributed to an operational frequency of up to 284 MHz (Altera Quartus II software) which is sufficient to encode high resolution videos in real-time.

Block matching motion estimation is the heart of video coding system. It leads to a high compression ratio, whereas it is time consuming and calculation intensive. Many fast search block matching motion estimation algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose an efficient hardware architecture of the fast line diamond parallel search (LDPS) algorithm with variable block size motion estimation (VBSME) for H.264/AVC video coding system. The design is described in VHDL language, synthesized to Altera Stratix III FPGA and to TSMC 0.18 μm standard-cells. The throughput of the hardware architecture reaches a processing rate up to 78 millions of pixels per second at 83.5 MHz frequency clock and uses only 28 kgates when mapped to standard-cells. Finally, a system on a programmable chip (SoPC) implementation and validation of the proposed design as an IP core is presented using the embedded video system.

Motion estimation is a highly computational demanding operation during video compression process and significantly affects the output quality of an encoded sequence. Special hardware architectures are required to achieve real-time compression performance. Many fast search block matching motion estimation (BMME) algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose three new hardware architectures of fast search block matching motion estimation algorithm using Line Diamond Parallel Search (LDPS) for H.264/AVC video coding system. These architectures use pipeline and parallel processing techniques and present minimum latency, maximum throughput and full utilization of hardware resources. The VHDL code has been tested and can work at high frequency in a Xilinx Virtex-5 FPGA circuit for the three proposed architectures.

In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.

As the new generation standard of video coding, the High Efficiency Video Coding (HEVC) is intended to provide significantly better coding efficiency than all existing video coding standards. One of his improvements is the encoding process of the structure block. It was established that this process requires high computing power because it is performed using all the possible depth levels and prediction modes to find the one with the least rate distortion (RD) cost using Lagrange multiplier. To reduce the computational complexity, fast coding unit size decision algorithms were proposed and implemented in HM. These algorithms can significantly reduce computational complexity while maintaining almost the same performance as the original HEVC encoder.

This paper describes efficient hardware architecture for the deblocking filter used in H.264/AVC baseline profile video coding standard. The deblocking filter is a computationally and data intensive tool leading to an increased execution time of both encoding and decoding processes. In fact, we propose a novel edge filter ordering which needs 64 clock cycles to filter a Macroblock (MB). A specified memory organization is also applied in order to avoid unnecessarily waiting for availability of the pixels that will be filtered. The proposed architecture includes both pipelining and parallel processing techniques and is implemented in synthesizable HDL. This hardware is designed to be used as module of a complete H.264/AVC decoder which the functionality was validated on Nios II at 100 MHz.

This paper presents the hardware design of a unified architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional (2-D) transform for the HEVC standard. This architecture is based on fast integer transform algorithms. It is designed only with adders and shifts in order to reduce the hardware cost significantly. The goal is to ensure the maximum circuit reuse during the computing while saving 40% for the number of operations. The architecture is developed using FIFOs to compute the second dimension. The proposed hardware was implemented in VHDL. The VHDL RTL code works at 240 MHZ in an Altera Stratix III FPGA. The number of cycles in this architecture varies from 33 in 4-point- 2D-DCT to 172 when the 16-point-2D-DCT is computed. Results show frequency improvements reaching 96% when compared to an architecture described as the direct transcription of the algorithm., {"references":["Gary J.Sullivan, Pankaj Topiwala, and Ajay Luthra, \"The H.264/AVC\nAdvanced Video Coding Standard:Overview and Introduction to the\nFidelity Range Extensions\" SPIE Conference on Applications of Digital\nImage Processing XXVII. Special Session on Advances in the New\nEmerging Standard: H.264/AVC, August, 2004.","Gary J. Sullivan and Jens-Rainer Ohm \"Recent developments in\nstandardization of high efficiency video coding (HEVC)\". SPIE\nConference on Applications of Digital Image Processing XXVII.\nProceeding of SPIE Volume 7798, August,2010.","Gary J.Sullivan, Jens-Rainer Ohm, Woo-Jin Han, \"Overview of the\nHigh Efficiency Video Coding (HEVC) standard\" IEE Trans. On\nCircuits and Systems for Video Technology, December 2012.","Ashfaq Ahmed, Muhammad Awais, Martina Maurizio and Guido\nMasera \"VLSI Implementation of 16-point DCT for H.265/HEVC using\nWalsh Hadamard Transform and Lifting Scheme\". IEEE 14th\nInternational Multitopic Conference. December 2011.","Ricardo Jeske, José Cl├íudio de Souza Jr., Gustavo Wrege, Ruhan\nConcei├º├úo, Mateus Grellert, J├║lio Mattos and Luciano Agostini \"Low\nCost and High Throughput Multiplierless Design of a 16 Point 1-D\nDCT of the New HEVC Video Coding Standard\" VIII Southern\nProgrammable Logic Conference (SPL), March 2012.","Muhammad Martuza and Khan A.Wahid \"Low Cost Design of a\nHybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and\nHEVC\" Hindawi Publishing Corporation ,VLSI Design,Volume 2012.","Jong-Sik Park, Woo-Jin Nam, Seung-Mok Han, and Seongsoo Lee. \"2-\nD Large Inverse Transform (16x16, 32x32) for HEVC (High Efficiency\nVideo Coding)\" Journal of Semiconductor Technology and Science,\nvol.12, June 2012.","Benjamin Bross, Woo-Jin Han Jens Rainer Ohm and Gary J.Sullivan\n\"JCT-VC-G1103 Working Draft 5 WD 5\", Novembre 2011.","Fatma Belghith, Hassen Loukil and Nouri Masmoudi \"Free\nMultiplication integer Transformation for the HEVC Standard\" The\n10th International Multi-Conference on Systems, Signals and Devices\n(SSD) March 2013, in press .\n[10] Antonio J. D├¡az-Honrubia, José Luis Mart├¡nez and Pedro Cuenca, \"\nHEVC:A Review, Trends and Challenges\" 2nd Workshop on\nMultimediaData Coding and Transmission, September 2011."]}

This paper presents an optimized algorithm to compute the 4×4, 8×8 and 16×16 efficient one-dimensional (1-D) transform. The suggested algorithm is based on fast integer transform algorithms for the HEVC standard. Based on the similarity in the transform matrix operations and the symmetric properties, the efficient fast 1-D algorithms are developed. The developed architecture is designed only with adders and shifters. Therefore, the computational complexities of the proposed algorithm are smaller than those of the direct method while keeping similar quality.