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Transistors and ICs built in several different captive and commercial facilities were exposed to moisture, irradiated, and annealed. The moisture exposures were performed using highly accelerated stress test (HAST) at 130[degrees]C and 85% relative humidity. Irradiation of n-channel transistors exposed to HAST followed by a long-term anneal resulted in some increase in interface-trap and oxide-trapped charge buildup. However, exposing p-channel transistors to HAST preirradiation resulted in extremely large and unexpected voltage shifts immediately following irradiation. They were observed for devices with either doped oxide or nitride final chip passivation. Because of this, nitride passivation may not be sufficient to prevent [H.sub.2]O from causing enhanced radiation-induced degradation over long time periods in some devices (e.g., commercial devices with nitride final chip passivation packaged in plastic packages). The smaller voltage shifts for the n-channel transistors may be related to the formation of phosphosilicate glass (PSG) overlying the sources and drains of the n-channel transistors impeding the diffusion of moisture to the gate oxides. It is shown that, the large radiation-induced voltage shifts for the p-channel transistors can lead to enhanced IC parametric degradation and functional failure at lower radiation levels. Large increases in radiation-induced field oxide leakage current were also observed for transistors exposed to HAST preirradiation. Transistors were also annealed (prior to irradiation) and irradiated in [H.sub.2]. Approximately the same level of radiation-induced degradation was observed for n- and p-channel transistors suggesting that the diffusion kinetics for [H.sub.2] diffusion are considerably different than for [H.sub.2]O diffusion. These results raise the concern that exposure of devices to moisture or hydrogen can lead to long-term radiation-induced aging effects. Index Terms--Aging effects, hydrogen exposure, ionizing radiation, moisture exposure, MOS radiation effects.

The radiation hardness of nominally identical SRAM test chips fabricated in five commercial foundries is examined. Large variations in single-event latchup and total dose response are observed. The softest SRAMs fail functionally at ~200 krad(Si[O.sub.2]) and have a fairly large single-event latchup cross section. This is in contrast to the hardest foundry split which is nearly immune to single-event latchup at room temperature, and remains functional to a total dose of 400 krad(Si[O.sub.2]). Three of the splits show a similar increase in radiation induced leakage current, which is dependent on both the characterization bias as well as the pattern written to the memory array. The other two splits show neither a pattern nor a bias dependence on the leakage current. Heavy-ion microbeam experiments confirm that the most latchup sensitive area of these SRAMs is the peripheral circuitry, not the memory array itself. Qualification and hardened-by-design integrated circuit implications are discussed. Index Terms--Commercial foundry, COTS, heavy-ion, leakage current, neutron, proton, radiation effects, radiation response, SEL, SEU, single event, SRAM, total-dose.

To explore the impact of temperature on the post-irradiation response of ICs, we characterized the temperature response of transistors, SRAMs, and a custom mixed-signal ASIC. Devices were irradiated at room temperature and electrically characterized post irradiation as a function of temperature. Devices exhibit significantly more parametric degradation when characterized at elevated temperatures. In addition to parametric degradation, it is demonstrated that post-irradiation elevated temperature characterization can also induce functional failures at significantly lower total dose levels than at room temperature. As a result, to ensure system functionality, it is essential that devices be characterized over the full system temperature range pre- and post-irradiation. Recommendations for incorporating temperature testing into a hardness assurance test method (i.e., Method 1019) are suggested. Methods for minimizing the detrimental effects of elevated temperature anneals on hardness assurance testing are also discussed. Index Terms--Hardness assurance testing, integrated circuit radiation effects, integrated circuit reliability, radiation effects, radiation hardening (electronics).

Final chip passivation layers are shown to have a major impact on the total dose hardness of bipolar linear technologies. It is found that devices fabricated without passivation layers do not exhibit enhanced low-dose-rate sensitivity (ELDRS) or pre-irradiation elevated-temperature stress (PETS) sensitivity, whereas devices from the same production lot fabricated with either oxide/nitride or doped-glass passivation layers are ELDRS and PETS sensitive. In addition, removing the passivation layers after fabrication can mitigate ELDRS and PETS effects. ELDRS and PETS effects do not appear to be inherently related to circuit design or layout, but are related to mechanical stress effects, hydrogen in the device, or a combination of the two. These results suggest that proper engineering of the final chip passivation layer might eliminate ELDRS and PETS effects in bipolar integrated circuits. Index Terms--Bipolar linear-integrated circuits, enhanced low-dose-rate sensitivity, hardness-assurance testing, integrated-circuit reliability, integrated-circuit testing, mechanical stress, passivation layers, pre-irradiation elevated-temperature stress, radiation effects, radiation hardening (electronics), radiation response, reliability screens, thermal cycling, thermal-stress effects, thermal stresses.

Generally good agreement is obtained between the single-event output voltage transient waveforms obtained by exposing individual circuit elements of a bipolar comparator and operational amplifier to an ion microbeam, a pulsed laser beam, and circuit simulations using SPICE. The agreement is achieved by adjusting the amounts of charge deposited by the laser or injected in the SPICE simulations. The implications for radiation hardness assurance are discussed. Index Terms--Bipolar analog, comparators, laser beams, integrated circuit, ion beams, ion microbeams, ionization, operational amplifiers, radiation effects, single event transient, transient response.

The geometric component of charge pumping current was examined in n-channel metal-oxide-silicon field effect transistors (MOSFETs) following low-temperature irradiation. In addition to the usual dependencies on channel length and gate bias transition time, the geometric component was found to increase with radiation-induced oxide-trapped charge density and decreasing temperature. A postirradiation injection of electrons into the gate oxide reduces the geometric component along with the density of oxide-trapped charge, which clearly demonstrates that the two are correlated. A fit of the injection data to a first-order model for trapping kinetics indicates that the electron trapping occurs predominantly at a single type of Coulomb-attractive trap site. The geometric component results primarily from the bulk recombination of channel electrons that fail to transport to the source or drain during the transition from inversion to accumulation. The radiation response of these transistors suggests that Coulomb scattering by oxide-trapped charge increases the bulk recombination at low temperatures by impeding electron transport. These results imply that the geometric component must be properly accounted for when charge pumping irradiated n-channel MOSFETs at low temperatures. Index Terms--Bulk recombination, capture cross-section, charge pumping, Coulomb scattering, geometric component, hot electrons, interface trap density, irradiation, low-temperature, mobility degradation, MOSFET, oxide-trapped charge, trapping kinetics.

Eliminating radiation-induced parasitic leakage paths in integrated circuits (ICs) is key to improving their total dose hardness. Semiconductor manufacturers can use a combination of design and/or process techniques to eliminate known radiation-induced parasitic leakage paths. However, unknown or critical radiation-induced parasitic leakage may still exist on fully processed ICs and it is extremely difficult (if not impossible) to identify these leakage paths based on radiation induced parametric degradation. We show that light emission microscopy can be used to identify the location of radiation-induced parasitic leakage paths in ICs. This is illustrated by using light emission microscopy to find radiation-induced parasitic leakage paths in partially-depleted silicon on insulator static random-access memories (SRAMs). Once leakage paths were identified, modifications were made to the SRAM design to improve the total dose radiation hardness of the SRAMs. Light emission microscopy should prove to be an important tool for the development of future radiation hardened technologies and devices. [ABSTRACT FROM AUTHOR]