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As 1999 ended, IBM announced its intention to construct a one-petaflop supercomputer. The construction of this system was based on a cellular architecture--the use of relatively small but powerful building blocks used together in sufficient quantities to construct large systems. The first step on the road to a petaflop machine (one quadrillion floating-point operations in a second) is the Blue Gene®/L supercomputer. Blue Gene/L combines a low-power processor with a highly parallel architecture to achieve unparalleled computing performance per unit volume. Implementing the Blue Gene/L packaging involved trading off considerations of cost, power, cooling, signaling, electromagnetic radiation, mechanics, component selection, cabling, reliability, service strategy, risk, and schedule. This paper describes how 1,024 dual-processor compute application-specific integrated circuits (ASICs) are packaged in a scalable rack, and how racks are combined and augmented with host computers and remote storage. The Blue Gene/L interconnect, power, cooling, and control systems are described individually and as part of the synergistic whole.

Methods and tool sets have been developed to allow fluxless OLB of high lead count TAB (tape automated bonding) components. The hot air thermode (HAT) is such a fluxless process. It can be used for most SMT components and is also well suited for TAB applications. HAT is a pick, place, and reflow system that uses high-velocity heated gas as the medium for solder melting and a dead reckoning method for package placement. Because of the particular tool/process integration employed by the HAT system, the technique does not require ovens with tightly controlled atmosphere and produces solder joints with excellent properties. Elimination of flux also eliminates flux application and cleaning steps during bonding, along with the solvents associated with the flux cleaning. Other advantages of this process include minimized emission during bonding and reduced bond corrosion, since corrosion due to entrapped flux residue is eliminated. The reliability of the solder joints produced by this method are discussed, along with process window data that demonstrate the use of the technique. >

This letter describes the first system level test vehicle in Josephson technology. The experiment consists of four circuit chips assembled on two cards in a high density, 3-dimensional, card-on-board package. A data path, which is representative of a critical path of a future prototype processor, was successfully operated with a minimum cycle time of 3.7ns. The path simulates a jump control sequence and a cache access in each machine cycle. This experiment incorporates the essential components of the logic, power and package portions of a Josephson technology prototype.

Packaging technology used to build the first system crosssection test vehicle in Josephson technology is described. A threedimensional modular card-on-board packaging approach has been selected to fabricate the test vehicle which incorporates all the essential features of the technology required to build a high performance processor prototype. Potential viability of the described packaging technology for the fabrication of such a prototype has been demonstrated by an experiment in which a critical data path has been successfully operated with a minimum cycle time of 3.7 ns.