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This paper presents a new parametric fault detection (PFD) approach for testing of linear analog circuits. It combines classified frequency-bands with amplitude weighting for fault controllability and test-points selection for fault observability. The test waveform sweeps on an applicable frequency-band instead of the whole band to stimulate parametric faults. The number of required samples is reduced, and the summation of samples from undesired bands is avoided. The test response is compacted for each band generating digital signature. The digital signature curve (DSC) is plotted for each component. A hybrid between MATLAB and PSPICE simulation is used to develop accurate worst case analysis (WCA). The relation between the classified DSC and the accurate WCA results in the enhanced PFD. It is found that the weighted sweeping-sinusoidal waveform is the best selection. The presented approach is applied to different linear analog benchmark circuits and shows the significant PFD improvement compared to previously published works.

The main purpose of this paper is to achieve ultra-low power Physical Unclonable Function (PUF) to meet the requirements for Internet of Things (IoT) applications. PUFs are promising hardware security primitives that are based on the uniqueness and the unclonability of the device's physical characteristics to provide a unique identifier for devices. PUFs can be used in device authentication and for secure key storage and generation. This paper presents Oscillator Collapse Physical Unclonable Function (OC-PUF), which is suitable for low power applications. The power consumption is reduced based on designing the most power-hungry modules in the OC-PUF. An Oscillator Collapse (OC) is designed to work in the near-threshold voltage region, which reduces the power consumption. More power reduction is achieved by designing a new Collapse Time Comparator (CTC). Due to the process variations, the oscillations period of each OC is different. The CTC generates the output response bit by comparing the oscillations periods of the two selected OCs. The simulation results demonstrate that the proposed OC-PUF can effectively reduce the power consumption. The proposed PUF is designed using 20 nm triple gate FinFET technology. The Simulation results for 1000 different chips with the same input challenge, show that the average power is 140 nW, with the worst case being 740 nW. The best case is 63 nW per challenge-response pair at supply voltage 0.5 V. The averaged reliability of the OC-PUF is 99.8%, at temperatures from -40 to 125 °C and supply voltage 0.5 ± 10%. The proposed OC-PUF decreases the power consumption while retaining high-performance metrics.

In this paper, a parasitic-design-aware simulation-based design tool is proposed for highly linear RF power amplifiers. The main aim of the proposed tool is to speed up the design process of RF power amplifiers. In addition, it provides accurate final designs taking into consideration the effect of parasitic components of both active and passive devices. The proposed tool relies on the knowledge of designing highly linear RF power amplifiers. Both the optimization steps and design methodology are presented in this paper. The proposed tool is verified by designing a highly linear RF power amplifier at three different frequencies (7 GHz, 10 GHz, and 13 GHz) using 65 nm technology node. The results show that an OP1 dB higher than 18 dBm, gain/S21 higher than 7 dB, and OIP3 higher than 24 dBm at 6 dB back-off power can be obtained.

Nowadays, flexible manufacturing is a vital aspect of factory automation. Focusing on developing countries, it is crucial to increase production line reliability at the lowest extra cost. There are two contributions presented in this paper. First, it is shown how to reduce the cost of a power station and still obtain the same power station reliability as that of a conventional 1-out-of-2 system. Second, the problem of the availability of spare parts (sensors) in developing countries is mitigated by swapping fault-tolerant architectures whenever different quality sensors are used. This can be easily done by housing the production line's controller as well as the sensors' error detection and recovery mechanism in an FPGA and using DPR for swapping mechanism without any costly hardware replacement. As an example, two fault-tolerant architectures are considered: TMR and 4-sift-out. Petri Nets are used to decide which one of the two architectures is more appropriate for a pre-determined level of reliability. Both TMR and Sift-out error detection and recovery mechanisms are synthesized and implemented on a XC7K160TFFV676-1 device.

This paper presents a new differential power oscillator design based on a differential class-E power amplifier. The designs use high power enhancement-GaN HEMT (e-GaN) for its fast switching time, low ON resistance and wide energy band gap properties. The target application is far field wireless power transfer for wireless charging applications. The initial guess for design parameters follows the well known Sokal approach then LTSpice simulator is used to finalize the design. The simulated output power of the power oscillator is 60 W at the 433 MHz ISM band with high DC-to-RF conversion efficiency. Effect of process and design parameter variability is considered to assess the design sensitivity to manufacturing tolerances in both active and passive components.

This paper presents a power oscillator design based on a class E power amplifier. The enhancement GaN HEMT is used for its fast switching time, low ON resistance and low temperature sensitivity. The presented circuit is designed to be used in far field wireless charging which is the 2nd generation in this type of chargers. The simulated output power of the power oscillator is 24.9 W at the ISM band of 433 MHz. Effect of design parameter variability is also studied.

In this paper, a simple closed-form model identifying the electrical behavior of a taper through silicon via (TSV) is reported. The model is based on the Transmission Line Method (TLM) and 3D electromagnetic simulations. The usefulness of the modeling approach is validated through measurements on some test structures over a wide range of frequencies from DC to 10 ​GHz. The substrate coupling and MOS effects are included in the electrical description of the 3D system as they are no longer negligible at high-frequency range operation. The efficient 3D-TLE (Transmission Line Extractor) by INL (Institute of Nanotechnology of Lyon) tool is used to extract the impedance of contacts and TSVs. Moreover, as an application of this extractor, a 26GHz/2 ​GHz bandwidth TSV based RF filter is proposed and designed.

This paper presents a new time-based ADC architecture that employs non-linearity cancellation and swing down scaling techniques to eliminate the non-idealities of the coarse and the fine VCO-based quantizers, respectively. The PWM pre-coded coarse quantizer allows for replacement of the DAC present in conventional two-step ADC architectures with simple logic gates and smoothing filters while relaxing the design constraints of the PWM pre-coded VCO based ADCs present in the literature. The entire power consumption of the ADC is 1.9mW under 1.2 V supply, while achieving an SNDR of 59 dB over 40 MHz bandwidth, yielding a conversion figure of merit of 33fJ/step.

The main purpose of this paper is to achieve as low as possible leakage current ( $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ ) to meet the requirements for ultra-low power (ULP) applications. The proposed methodology is based on studying the effect of the most effective FinFET design parameters that directly impact its leakage current. The parameters explored in this paper are the effective channel lengths $\text{L}_{\mathrm {eff}}$ , gate stacks, gate contact materials, and gate-sidewall spacers ( $\text{L}_{\mathrm {sp}}$ ). The results show that utilizing a symmetrical dual-k material for 7-nm underlap tri-gate FinFETs appreciably allows a sufficient ON current and low leakage current and hence low stand by power consumption. Specifically, the effect of spacer length $\text{L}_{\mathrm {sp}}$ and $\text{L}_{\mathrm {HK}}$ is investigated to get low leakage current keeping $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle ON}}}/\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ as high as possible. Moreover, the effective channel length in subthreshold conduction ( $\text{L}_{\mathrm {eff}}$ ) is maintained greater than the gate length ( $\text{L}_{\mathrm {g}}$ ) and the threshold voltage ( $\text{V}_{\mathrm {th}}$ ) is adjusted by the proper metal gate work function. The performance of the proposed n- and p-FinFET devices is verified using Sentaurus TCAD simulator from Synopsys. The resulted $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ is 17 pA/ $\mu $ m for n-FinFET and 14.7 pA/ $\mu \text{m}$ for p-FinFET which are the lowest leakage currents found in recent publications. The achieved $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle ON}}}/\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ ratio for both proposed devices is found to be $12.3 \times 10^{6}$ and $11 \times 10^{6}$ , respectively, which are comparable to the published data. These parameters are obtained for an appropriate choice of $\text{L}_{\mathrm {sp}}=10$ nm and $\text{L}_{\mathrm {HK}}= 5$ nm. In addition, the short channel effects variations with $\text{L}_{\mathrm {HK}}$ have been investigated.

This paper is proposing a new parametric fault detection technique of analog circuits based on frequency band classification. A sweeping-frequency testing signal is applied covering the analog circuit under test (ACUT) frequency bands. Instead of the overall summed responses (Signature), only a band digital signature is considered at which the component variation effect is dominant. As a result, the signature averaging due to the summation of unwanted (unaffected) signatures is avoided. The results show a significant parametric fault detectability increase over the previous work considering the all-band signature. Multi test point technique is a further enhancement that explores more component-affected bands and consequently, increases the parametric fault detectability.

In this paper, a design technique to improve low noise amplifier (LNA) performance is proposed. This technique is based on a new operating parameter (OP) of MOSFETs for radio frequency (RF) applications. This technique is used to optimize low noise amplifier (LNA) parameters for Ultra-Wideband (UWB) applications. The presented methodology predicts the optimum biasing point to maximize LNA performance. Simulation results show that the proposed methodology can increase the figure of merit (FoM) by 70% compared to traditional methodologies, without having a significant effect on either noise figure (NF) or linearity characteristics.

This paper presents a highly linear radio frequency front end (RFFE) receiver (Rx) with its frequency response characterized by having an adjustable shape, center frequency, and bandwidth (BW). The RFFE Rx output is sampled at an adjustable sampling rate to be fed to an ADC for further baseband processing. The architecture employs a generalization of noise cancelling theory to reduce the noise figure (NF) by including an auxiliary path besides its main path to be able to subtract the noise at the output. Simulated on 65 nm technology, this method is proved to reduce the NF from 6.5 dB to 3.5 dB for a selected filter impulse response and down to 2.3 dB in case of implementing a Sinc frequency response.

This paper presents a wireless sensor network for LED streetlight monitoring and controlling. The proposed system allows substantial energy saving through adequate controlling algorithm. It regulates the streetlight intensity according to the traffic and daylight state. A LED driver is designed to supply the LED with the required 80 W power. The drivers and the controller enable system controlling, monitoring and protection. The system can be widely applied in all places which need controlled lighting such as streets, stations, buildings.

In this paper, loss mechanisms of monolithic high frequency Class-E PAs are studied. The switching behavior is analyzed to understand the discrepancy between common design equations and optimal design values as frequency scales up. Analytical results are verified by spice simulations. In addition, a design recipe based on loss analysis and effective output duty cycle is proposed for mm-waves PAs to boost their power added efficiency ( PAE ). The design approach is adopted to compare different technology nodes including the 130 nm, 90 nm, and 65 nm bulk CMOS. Newer technologies show better PAE only at the mm-waves regime. Simulations show that the PAE is boosted from 31% to 40% when the proposed design methodology is applied at 60 GHz using the 65 nm node.

This paper illustrates the simulation, implementation and testing of an UWB transmitter based on Step Recovery Diode (SRD). For testing purposes, a square wave generator has been also implemented based on Colpitts oscillator and a clipping circuit that was used to trigger the monocycle pulse generator. The simulated output is a monocycle pulse waveform with 300 ps pulse width and acceptable symmetry in both amplitude and shape. Integrating the UWB transmitter and the Colpitts oscillator, the achieved output from this integration after implementation is a monocycle pulse waveform with 420 ps pulse width and acceptable symmetry in both amplitude and shape.

In this paper, a comprehensive comparison of TFET simulations using two TCAD simulators, Sentaurus and Silvaco TCAD, is presented. The comparison is fully cover various types of TFETs, either from the structure geometry or the materials point of view, which proved a framework for TFET designs and simulations. For Sentaurus TCAD, a dynamic nonlocal BTBT model is used for all simulations as it is proved a good calibration for experimental data or full quantum data taken from the literature. The BTBT model’s parameters are determined for different material and hetero-junctions structures where they can be used directly for any design or structure calibration. For the Silvaco simulator, a nonlocal BTBT model is utilized for calibration and its parameters are also provided. The study offers quick parameters data to be used directly, utilizing various materials without being involved in calibration difficulties.

In this paper, we propose splitting the piezoelectric material into smaller segments to change the resonant frequency of an energy harvesting cantilever. The effect of changing the length of each of these individual segments on the frequency response and output power is presented. The proposed system is simulated using Comsol. The simulation results indicate that the splitting idea is suitable for building an array of the piezoelectric tunable cantilevers. This will allow for wideband harvesters' implementation.

The management and control of the renewable energy sources in smart grid are currently the most challenging topics in this area of research. Since renewable energy sources are potentially located away from urban areas, cellular communications are most suitable for this purpose. In this paper, we propose an LTE-based priority and delay oriented multicast scheduling technique designed specifically for smart grid management purposes. Using multicast communications in smart grid is most suitable since various messages should be sent to multiple renewable energy sources simultaneously. This is to ensure that these sources are coordinated in performing the same action within a certain time constraint to avoid any power shortages or other issues within the system. We evaluate our proposed technique and compare it with other general purpose multicast scheduling techniques. Results show that the proposed technique offers an enhanced performance over other techniques in delivering smart grid traffic while maintaining good performance for the other real-time traffic, such as voice traffic, within the network.

A fast sense amplifier (SA) is required to face the challenges of sensing techniques in embedded memory systems in micro-controller units (MCU's) for automotive applications. This paper presents, compares and analyzes key benchmark performance parameters within state-of-the-art time-continuous sense amplifiers for time domain sensing. There are two main approaches to the design of time-continuous sense amplifiers in time domain sensing; differential based sense amplifier and common gate based sense amplifier. Comparative simulation results of state-of-the-art sense amplifier designs for multi-Ievel-cell (MLC) embedded memories in time domain are presented in 28 nm technology. High performance differential based SA with 40% lower sensing delay and 30% higher selectivity for stronger programmed cells compared to the state-of-the-art common gate approach for automotive SA designs with 28 nm technology is presented.

This paper presents an automatic-frequency-tuning RF energy harvester. The proposed self-startup system tracks the frequency of maximum input power automatically within its wide frequency range of operation from 1.65 GHz to 2.5 GHz. The system is mainly composed of two rectifying paths and a frequency tuning control loop. Implemented in a 130-nm CMOS technology, simulation results show power conversion efficiency (PCE) of the main path rectifier of 62% at 10-kΩ load resistance. The input power sensitivity of the main path is -18 dBm for output voltage of 0.5 V and a load resistance of 100 kΩ.

This paper presents a MOSFET model for ultra-low power radio-frequency integrated circuits (RFICs) design. In addition, we discussed the concept of the Operating Parameter (OP) as the main design parameter used to determine the operating point, from weak, via moderate, or strong inversion. The proposed OP based analytical model is applied to an LNA design (3–5 GHz) in 130 nm CMOS technology. Simulation results showed a minimum noise figure (NF) of 2.3 dB, max gain 9.6 dB and 0.25 mW power dissipation. The figure of merit (FoM) is found to be superior to previous design techniques.

In this paper, technology fundamental limits on the performance of stacked and classical Class E power amplifiers are studied. A current combined stacked injection locking technique is proposed in order to enhance both the output power and power-added efficiency (PAE). Based on this technique, a 60 GHz fully differential stacked power amplifier is designed in 65nm CMOS bulk process. The simulation results show an output power of 19.5dBm and PAE of 15.5%.

The use of wireless sensor networks to protect sensitive facilities or international borders has recently attracted more and more attention. It has become a high-priority issue in many countries. In addition to the physical fences built for stopping illegal intruders from crossing the border, smart fencing has been proposed to extend intrusion-detection capabilities. Event detection is a central component in numerous wireless sensor network applications. In spite of this, the area of event description has not received enough attention. The majority of current event description approaches rely on using precise values to specify event thresholds. However, these crisp values cannot adequately handle the imprecise sensor readings. Therefore, in this paper, a hybrid event-detection algorithm based on two layers of 12-bit-resolution fuzzy logic system is used, which significantly improves the accuracy of event detection. Each sensor node has sensors to improve the precision of the detection system, as well as reducing the false alarm rate especially in a noisy environment. The proposed system was modeled using Matlab and designed using VHDL. The proposed system’s VHDL code has been compared with the Matlab model, which provided very close results to this software-based controller model, and also with two other VHDL-based designs, results of which are also close and comparable to the proposed system. The proposed design is then implemented using a FPGA kit, and the prototype is connected to a graphical user interface. Finally, a testing experiment of this proposed system shows an event-detection ratio capability of 98.4 % and the false alarm ratio of 1.6 %.

This work represents a proof-of-concept for remote monitoring and control of fish farms using WSN (Wireless Sensor Networks). The system allows a 24/7 live monitoring of water quality (mainly Temperature, pH value and Dissolved Oxygen value) in fish farms. The system is remotely accessed through the Internet via Desktop PCs and Mobile Phones. The system has the capability of sending alarms via different methods (emails or website notifications) to fish farms administrators. Thus, allowing them to take appropriate measures by means of remote actuation of different utilities installed in the fish tanks. The system aims to reduce the accidental mortality of fish which might happen due to water pollution or sudden environmental changes.

In this paper, a design methodology to enhance the performance of low-noise amplifier (LNA) is presented. The methodology proposes a new operating parameter (OP) by using the drain-source saturation voltage (VDSsat) as an additional design parameter. This OP reaches a maximum value close to the threshold voltage (V t ) in moderate inversion region. A 3–5 GHz ultra-wideband (UWB) common gate design is used as an example to show the effectiveness of the proposed methodology. Simulation results show that the proposed methodology can reduce power consumption by 22% and increase the figure of merit (FoM) by 30% compared to traditional methodology, without having a significant effect on either noise figure (NF) or linearity characteristics.

The behavior of 6T SRAM cells in presence of process variability for physical unclonable functions (PUFs) is analyzed on the 16 nm FinFET technology. Both systematic and random threshold voltage variations are considered in this analysis. Randomness prosperity of the secret keys generated from the SRAM cell is tested. Supply voltage ramp-up impact on the cells start-up values is also analyzed at different mismatch amounts.

The electrocardiogram (ECG) signal is the recording of the electrical activity of the human heart. The compression of the ECG signal is highly beneficial for the purpose of wireless transmission as well as storage. A new algorithm for ECG signal compression is proposed in this paper. The algorithm is based on the observation that the ECG signal in the steady state is very stable with highly correlated successive pulses. Thus, the algorithm performs differential encoding between each new pulse and a stored reference pulse. This idea is inspired by the video compression techniques where the inter-frame changes are very limited. Therefore, high signal compression ratio can be obtained. The performance of the introduced technique is evaluated and compared to the state-of-the-art techniques. The performance is characterized by the compression ratio (CR) and the percentage of root mean square difference (PRD). The algorithm achieved a CR of 105 with PRD below 1.3%. Moreover, the comparison with other existing ECG compression methods demonstrated the superiority of the proposed algorithm.

In this paper, a new broadband low noise amplifier (LNA) is proposed. The LNA utilizes a composite NMOS/PMOS cross-coupled transistor pair and a difference amplifier to in-crease the linearity while reducing the noise figure. The introduced approach provides partial cancellation of distortion and noise generated by the input transistors, hence, degrading the overall distortion. The LNA is implemented by using the UMC 130 nm CMOS technology node. The post simulation shows that a conversion gain equals 16.2 dB across 0.05–3.1 GHz frequency range, an IIP3 is +9.2 dBm, and minimum and maximum noise figure are 1.4 dB and 2 dB, respectively. The LNA consumes 32.4mW from 1.8 V supply and occupies an area of 0.075 mm2.

Upon tightening new regulations, the demand for using smart wireless sensing for health, safety, and surveillance applications of nuclear installations is growing rapidly. To help with the developments, this paper describes the design of a practical small-scaled wireless sensor network (WSN) that allows a smart real-time monitoring of radiation levels at nuclear facilities. A wireless system compiled with a radiation sensor and associated peripherals been developed and implemented upon ZigBee technology using TI CC2530 chip. The radiation sensor uses a Geiger Muller tube as a reliable detector for the radioactive particulates in the gaseous effluent vented from nuclear facilities. The WSN allows the operators to record and control the radiation levels emitted to the environment and it is supported with a warning system, for the early detection of radiation release. However, building a reliable wireless sensing system with an effective coverage, especially for indoor applications, requires professional planning and proper investigation. In this paper, a procedure to investigate the wireless sensing coverage is reported where a ray-tracing simulator is adopted to enable the wireless node placement prior to the deployment. A real test scenario has been implemented based on the built wireless node to examine network coverage inside a 60-m hallway and results have been compared with simulations showing a 100% packet reception ratio.

Pressure sensing in harsh environments poses many difficulties. The major challenge is implementing a sensor interface circuit capable of operation at high temperatures ( 300°C) for extended periods of time. Conventional, siliconbasedelectronics are not suitable for operation in such conditions due to their sizable leakage currents and junction instability. Inthis work, a wireless solution based on silicon carbide electronics is presented. The proposed solution follows a simple design procedure and exhibits robustness to the large process variations typically associated with silicon carbide technology.

The use of wireless sensor networks to protect sensitive facilities or international borders has recently attracted more and more attention [1-3]. It has become a highpriority issue in many countries. In addition to the physical fences built for stopping illegal intruders from crossing the border, smart fencing has been proposed to extend intrusion detection capabilities. Event detection is a central component in numerous wireless sensor network (WSN) applications [4, 5]. In spite of this, the area of event description has not received enough attention. The majority of current event descriptionapproaches rely on using precise values to specify event thresholds [6, 7]. However this crisp values cannot adequately handle the imprecise sensor readings. Therefore, In this paper, Event-detection algorithm based on two layers fuzzy Logicsystem (FLS) is used, which conveys the idea of using fuzzy values instead of crisp ones which significantly improves the accuracy of event detection. Each sensor node has an acoustic signal sensor and one-axis acceleration sensor to improve the precision of the detection system, as well as reducing false alarm rate specially in a noisy environment.

Signal integrity analysis is usually performed solely in the time domain. The traditional way to include the frequency-dependent elements, like interconnects, is to convolve their impulse response with the input and the other circuit element models to obtain the overall response. This method is inefficient in terms of speed of computation and might lead to stability problems. Therefore, transforming all the specifications of system and signals defined in the time domain to the frequency domain and performing a complete frequency-domain based signal integrity analysis, would simplify and speed up the process and make it effectual. In this paper, the relationship between clock signal deviations in the time domain -for example the undershoot, overshoot, and rise and fall times- and their frequency-domain features was quantified, both numerically and analytically. The proposed models are modeled and simulated in Matlab; whereas a point-to-point communication model is built on Keysight's Advanced Design System to justify these models.

A low noise chopper instrumentation amplifier (IA) with proposed feed-forward ripple suppression (FFRS) technique is presented in this paper. Employing a feed-forward path followed by a ripple suppression transfer function, the proposed technique eliminates the output chopping ripples significantly. In addition, ripple suppression is achieved without much current consumption overhead. The chopper IA is designed for high input impedance along with minimized noise floor essential for signal conditioning circuits of biopotential signals. Simulation results, using UMC 65 nm CMOS technology, reveals that the proposed FFRS technique achieves an input referred ripple equals to 0.28 μV corresponding to 68 dB of ripple suppression. Moreover, the DC input impedance of the chopper IA is 6 GΩ. The overall chopper IA achieves an input noise power spectral density (PSD) equals to 55 nV/√Hz and bandwidth equals to 1 kHz with supply voltage equals to 1.2 V.

A low-power current-reused LC VCO circuit is implemented in 65-nm CMOS technology. The VCO covers frequency ranges (9.2 → 10.4) GHz and (10.6→12.4) GHz. The VCO core consists of two parallel active sections to adapt Gm with the operating frequency. Adaptive body-biasing technique using a new amplitude detector circuit is proposed. Switched varactor-bank circuit with boosted on-voltage is implemented to achieve a wide tuning range of 29% without sacrificing the phase noise and power. The VCO consumes 0.93 mA from 1.1-V supply at 12 GHz. The post-layout simulated phase noise is −105.3 dBc/Hz at 1 MHz offset from 12-GHz carrier frequency. The proposed VCO achieves FOMt of −196.35 dBc/Hz.

A chopper capacitive feedback instrumentation amplifier (CCFIA) with proposed input impedance boosting technique is presented. Using a negative capacitance circuit, the proposed boosting technique achieves higher input impedance across frequency when compared to traditional approaches without injecting current back to a biopotential electrode attached to human body. Moreover, boosting the input impedance is at no expense of the input referred noise of the CCFIA. A ripple reduction loop (RRL) is employed for suppressing the output chopping ripples. Also, a DC servo loop is designed for filtering out the electrode DC offset. Simulation results, using UMC 65 nm CMOS technology, demonstrate that the proposed input impedance boosting technique achieves much higher than 2 GO input impedance. In addition, the maximum input referred ripple is less than 1 μV. The CCFIA can tolerate up to 20 mV of electrode DC offset. The overall CCFIA achieves an input referred noise PSD equals to 35 nV/√Hz and bandwidth equals to 450 Hz with supply voltage equals to 1.2 V.

In this paper, high frequency limitations of injection locked power amplifiers (ILPAs) are studied. A new phase alignment technique is proposed to minimize the loss of both injecting and oscillating devices at tens of gigahertz. Analytical results are verified by spice simulations. The theory is carried to design an ILPA at 60 GHz. Comparison is performed with the Class-E PA, and the cross-coupled ILPA. Post-layout simulation results show that the power added efficiency (PAE) of the phase aligned ILPA is the highest of the three, reaching 40% while it is 32% and 24% for the cross-coupled ILPA and the Class-E PA respectively, using the standard 65 nm CMOS node.

A charge pump circuit to minimize current mismatch and current variation over a wide voltage compliance range is proposed. A feedback loop is used to cancel both deterministic and random mismatches between charging and discharging current to minimize PLL reference spurs and static phase offset. A current compensation circuit is used to minimize current variation to avoid bandwidth variation and loop instability. The circuit can operate at low supply voltage. The power overhead due to added circuitry is 3.36% making it suitable for low-power and low-voltage applications. The proposed current-steering charge pump circuit achieves mismatch lower than 0.44% over the output voltage range from 0.06 V to 0.85 V. Also the current variation is reduced to less than 1.19% when the output voltage varies from 0.06 V to 0.85 V in the 65 nm CMOS process with 1 V supply.

UWB printed monopole antenna with embedded reconfigurable multiband frequency notch function is proposed. Frequency notch is achieved by using a ground-plane slot. Lumped capacitors are added to miniaturize the slots and hence take advantages of adding more slots to reject more bands without increasing the overall size of the antenna. Added capacitors are also enhancing band rejection and introduce tunable capability. Reconfigurabiltiy is introduced in a way you can independently switch ON/OFF the band notches by mean of RF switches. Investigation on the effect of lumped capacitor is presented. Simulation results of S11 for different states and radiation patterns at different frequencies are also presented. Simulation results are verified with measurements. The commercial CST Microwave Studio 5 is used for simulations and performance optimizations. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 2076–2080, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25365

We present a wideband architecture for DeltaSigma modulators using a single active stage and two switched capacitor passive stages. The mixed active-passive implementation has performance advantages over traditional switched-capacitor (SC) or continuous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios. Design insensitivity to clock jitter and process variations is achieved by the good choice of the modulator architecture. The proposed modulator is designed in 0.13-mum CMOS technology and meets all major requirements for application in IEEE 802.16 wireless MAN receivers. Circuit simulations show that the modulator with a single bit quantizer consumes 5.5 mW from a 1.2-V power supply and achieves a 9-bit resolution over a 10-MHz bandwidth at an OSR of 32. Good performance is also achieved for lower bandwidth applications.

In this paper, an RF power amplifier intended for Class 1 Bluetooth application is designed using 0.35mum CMOS technology. A layout-aware macromodel for the BSIM3v3 MOSFET transistor for RF applications including substrate effect is investigated and used in this design. The model is validated for a 0.35mum CMOS process using a transistor with total width of 90mum and 18 fingers and it shows an excellent agreement with the ft, and S-parameter measurement data up to 6GHz. Effect of pads and bond wires are also taken into consideration during the design process of the PA. After post-layout simulations, the amplifier delivers an output power of 19dBm with 33.7% PAE under 3.3V supply. This amplifier has a power control feature. Its two stage circuit utilizes a cascode configuration in its first stage in order to use its bias pin as a power control input for the amplifier. Using this method, the power control range can be decreased down to 1.4 dBm which satisfies the Bluetooth standard. The chip is fabricated and is currently under testing

In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply. The chip performance achieves S11 below -10 dB across the entire band and a minimum noise figure of 2.55 dB. The simulated third-order input intercept point is -2.7 dBm. The voltage gain reaches a peak of 11.2 dB in-band with an upper 3-dB frequency of 3.8 GHz, which can be extended to reach 6.2 GHz using shunt inductive peaking. A figure of merit is devised to compare the proposed designs to recently published wideband CMOS LNAs

This paper presents a 20-GSps low-power ADC-based equalizer for high speed serial links receiver. Digital receivers are recently adopted to overcome the challenges of power, delay and mismatches facing circuits in the analog domain besides utilizing benefits of the digital domain of scaling, adaptation algorithms, calibration and noise immunity. The ADC-based equalizer is designed and simulated in a 65-nm CMOS technology and dissipates 15.5 mW in the ADC and 0.45 mW in the discrete-time linear equalizer from 1-V supply. Low power consumption is achieved by using interleaving in ADC architecture, utilizing charge-steering concept, sharing single reference ladder across the four interleaved branches of ADC, and using a novel proposed design for the comparator itself in the Flash ADC besides using the novel Discrete Time Linear Equalizer-DTLE-circuit.

This paper presents a methodology for monitoring the heart activity by capturing two ECG leads and sending the captured data to a monitoring unit using ZigBee technology and comparing the results with wired ECG. The received leads are stored and processed to get another four leads.

3D integration of digital designs presents an important paradigm shift that introduces several benefits in speed, power, area, and footprint. Significant work has been done so far to enable CAD tools to handle 3D designs and account for TSVs. Yet, it is not as mainstream as conventional planar CAD tools. This work explores enabling existing flow and tools to handle full 3D designs without introducing drastic changes or excessive computations. It focuses on full 3D design STA with routing parasitics for its critical importance in the digital design flow. It proposes and implements an STA framework that efficiently handles full 3D extracted digital designs, as well as, regular planar ones. It presents details on the TSV extraction model, connectivity representation, and delay calculations. The framework can be easily adapted for placement and routing optimizations as well.

In this paper, loss mechanisms of monolithic high frequency Class E PAs are studied. The switching behavior is analyzed to understand the discrepancy between common design equations and optimal design values as frequency scales up. Analytical results are verified by spice simulations. In addition, a design recipe is proposed for mm-Waves PAs. The design approach is adopted to compare different technology nodes including the 130 nm, 90 nm and 65 nm bulk CMOS. Newer technologies show better power added efficiency (PAE) only at the mm-Waves regime. Simulations show that the PAE is boosted from 31% to 40% when the proposed design methodology is applied at 60 GHz using the 65 nm node.

In this paper, a noise cancelling technique is proposed for envelope detectors. The noise cancelling technique reduces the noise introduced by the devices of the envelope detector to achieve higher signal-to-noise ratio without the need to increase the power consumption. To our knowledge, this is the first envelope detector with noise cancelling technique. Theory as well as simulation results are demonstrated in this paper. The proposed envelope detector is simulated using 65 nm CMOS technology node. Simulation results shows that the sensitivity of −60 dBm is obtained at an RF frequency of 2.4 GHz for a data rate of 2 Mbps while consuming 22 μW from 1 V supply.

In this work we present a simulation study for single events in n/sup +/-p junctions. The study investigates the variation of both the single-event induced current and the consequent collected charge with bias, substrate doping and minority carrier lifetime. We show that the minority carrier lifetime is the key factor in determining the amount of the total collected charge which is a new finding as per the authors' knowledge. We also present a brief study of the collection mechanisms and their dependence on the doping and bias. We finally conclude by the verification of a model that we had previously presented for the funneling-assisted collection current.

A noise analysis of bipolar harmonic mixers (BHM) used for direct-conversion receivers is presented in this paper. Analytical and simulated results for the transfer function of the mixer are presented. Simple analytical expressions describing noise contribution from all sources are derived. Estimation of flicker noise quite agrees with harmonic-balance simulation results. Based on the derived expressions, total time average noise power spectral density (PSD) at the output is compared with simulation results. For the recommended regions of operation, error is less than 20%. The overall BHM noise figure (NF) is calculated and optimized based on a simple extracted formula. Errors introduced by analysis remain within a 1.5-dB margin with respect to simulation results. The validity of analysis for high frequencies is justified. The effect of flicker noise coefficient on the overall mixer NF is compared for different available processes.