Search

A novel double-density hemi-cylindrical (HC) structure 3-D NAND Flash architecture was demonstrated (Lue et al. , 2019). HC 3-D NAND squeezes the gate-all-around (GAA) hole in one direction, followed by a slit cut to split the GAA device to produce twin cells, thus creating >2.5 times of memory density than standard GAA 3-D NAND at the same stacking layer. It is demonstrated that the extremely scaled HC 3-D NAND shows excellent 100k endurance and large memory window >10 V. Contrary to the standard GAA 3-D NAND, HC device has special edge effect issue. For taller HC device, a “wake-up” effect (Du et al. , 2020) by an initial strong –FN erasing can introduce gate injected electrons that electrically suppress the parasitic edge and in turn “wake-up” the device to produce a larger programming window. TCAD simulation clearly shows asymmetrical ${E}$ -field distribution from bottom oxide field to top oxide field at Region I (HC tip) and Region II (bottom edge). Through the comprehensive investigation of HC device “wake-up” effect and strong –FN for initial reset, the variation of cell to cell operation window is minimized and aligned to extremely scaled “hero” HC devices that enjoy field enhancement effect (Hsu et al. , 2007). Our results suggest a promising path of 3-D NAND device toward aggressive dimension scaling and large memory window.

A novel confined nitride (SiN) charge trapping 3-D NAND flash with excellent postcycling retention performances was demonstrated. Using a uniform sidewall lateral recess in the 3-D stack followed by a SiN pull-back process to isolate the SiN trapping layer in a self-aligned way is critical to facilitate this structure. Lower erase saturation ${Z}$ -direction. Therefore, this structure is in favor of the larger memory window (>10 V) design. Random telegraph noise (RTN) characteristics are comparable to the traditional 3-D NAND device with 100 years at 60 °C and even longer at room temperature. Moreover, superior post-1K-cycled multilevel cell (MLC) retention was also illustrated, which even sustains 150 °C and one-week baking. Therefore, the device has the potential to meet the low-cost long-retention archive memory applications.

In this work, we report two performance enhancement schemes for single-gate vertical-channel (SGVC) 3-D NAND Flash. The first one features a programming (PGM) waveform where the bias of the dummy wordline (DWL) is raised in a two-step manner so that the resultant disturbance that the DWL and edge WL suffer is appreciably alleviated. The second scheme takes advantage of a unique behavior termed “self-boosting-enhanced-PGM” mechanism in the pair- bitline PGM method to deal with the slow PGM bits and achieve a much lower bit error rate as a consequence. By using these two approaches, the bit error rate after multilevel cell (MLC) operation can be substantially improved by 82%.

Recently, we have developed a novel vertical split-gate Flash (or vertical 2T NOR) architecture in a n-channel device. In this work, we further develop the p-channel device counterpart, and demonstrate 4 different electron and hole injection methods, including band-to-band tunneling-induced hot-electron (BBHE), +FN electron, source-side injection hot-hole (SSIH), and-FN hole injections. The split-gate Flash allows both over-erase and over-program supported by the select-gate (SG) transistor. Bit-alterable operations are possible, thus providing very flexible and versatile memory operations. Various combinations of P/E cycling endurance are studied, and it is found that BBHE electron together with-FN hole injections produce the best match for endurance, while other combinations especially with SSIH induce more degradations. The advantages of this device are (1) Both n- and p-channel Flash can be fabricated on the same wafer; (2) The Flash transistors enjoy high ON/OFF ratio> 7 orders, good for a re-configurable switch; (3) Large tunable Vt window of 6V. These advantages offer good potential of realizing functional memories, such as being used in a reconfigurable circuit, especially for the connection block in a field programmable array (FPAA or FPGA).

Recently, we proposed a novel 3D AND-type Flash memory [1]–[3] architecture for 3D NOR Flash solution. In this work, we further propose a “write-in-place” (or “in-place write”) operation (like EEPROM) and demonstrate the feasibility. “Write-in-place” is to provide the same erase unit (page erase) as the program unit (page program). Thus to overwrite a page data the users just need one page erase followed by the page program, without the need to deal with a large erase unit (like NAND and NOR Flash memories). The in-place write does not require complex GC (garbage collection) algorithms by system controller, and can eliminate the write amplifications effect and improve the QoS (quality of service) of system performances. After optimization of BE-MANOS charge-trapping device, the in-place page write time can be minimized to around 110usec. Small neighbor-WL interferences, free from pattern loading effects and hot-carrier disturbs are merits of 3D AND architecture to enable write-in-place. We also suggest the future extensions of integrating ferroelectric memory FeFET device in the 3D AND architecture to further boost the in-place write speed to nearly 1 micro second at lower write voltages (∼5V).

In this paper, we will first introduce the recently developed 3D AND-type Flash memory [1]- [3] for 3D NOR Flash and CIM solutions. 3D AND inherits the processing advantages of 3D NAND Flash that can produce hundreds of layers eventually, while the memory transistors are connected in parallel to enable much larger sensing current (>6uA) for fast read like NOR Flash (contrary to the slow-read of NAND Flash). Good device performances in endurance and retention are demonstrated. In addition to the NOR Flash applications, 3D AND has potential to provide CIM solutions. The major device advantages of 3D AND for CIM are: (1) 3D high-density CIM enhances the TOP/s/mm2 performances; (2) Large transistor Ion/Ioff ratio > 4 orders; (3) Flexible and tunable Icell ranging from 150nA to 1.5uA, with tight distribution (

A spiking neural network (SNN) with non-volatile memory synapses can facilitate an ideal analog approach with low power consumption for intelligent applications. However, reliability issues would arise due to the characteristics of Non-Volatile Memory synapses operating under the limited size of a neural circuit component called membrane capacitor, resulting in low precision MAC. Through a simulation study, we identified several important criteria of the memory synapses that affect performance of the SNN for the membrane capacitor size of 1pF. (1) The required ON-OFF ratio of synapse needs to be >1000 to preserve classification accuracy. (2) Low on-current Ion (

We develop a vertical split-gate Flash memory to enable embedded Flash (eFlash) scaling. The device features much smaller cell size ( 30 (at 4-bit resolution, MAC only) and high TOPS/mm2~1 can be achieved. The excellent TOPS/mm2 suggests an effective way to boost the computing performances by designing more multi cores to parallelly compute the DNN using the high-density and low-power CIM memory devices and save data (weight) movements by ~85%.

The analog neuromorphic circuits with functional memory devices are considered as an ultimate ideal approach to mimic the human brain for artificial intelligence (AI). The spiking neural network (SNN) with integrate-and-fire (IF) circuit is the classic building block theoretically, but so far it is very difficult to find ideal devices to realize the SNN circuit. In this work, we propose a novel functional memory that is enabled by a novel thyristor, which features super-steep slope (S.S.~0.015mV/dec), large ON/OFF ratio (> 5 orders), and tunable V th range (0~3V). These are very ideal to meet the IF circuit requirements. Circuit and network simulations indicate that the gate-controlled thyristor (GCT) device for the IF circuit can realize high accuracy and performance for image recognition SNN. Our novel SNN architecture with the GCT device can provide good energy efficiency (equivalent to 181TOPS/W for accumulation operations), good error tolerance to V th variations (~10% range), and substantially smaller circuit area than that using conventional CMOS devices for IF circuit.

We demonstrate a 3D stackable AND-type Flash memory architecture for high-density and fast-read non-volatile memory solution. The device is based on a gate-all-around (GAA) macaroni thin-body device, with two vertical buried diffusion lines by N+ doped poly plug to connect all memory cells in a parallel way to achieve 3D AND-type array. High sensing current >6uA enables fast Tread ~100ns like NOR Flash, while the structure can enable hundreds of stacked layers eventually. Large transistor ON/OFF ratio of >5 orders, >5V Vt memory window, 100K Endurance, read-disturb free property, and small RTN are demonstrated in our 3D architecture using the BE-MANOS charge-trapping device. This architecture is promising to realize high-density 3D NOR Flash and future storage-class memory (SCM).

NOR Flash has stopped scaling for many years. However, recently there are increasingly new demands of NOR Flash in various 5G and IoT applications or wearable devices that strongly require new technology advancement of NOR. In this work, we developed a new vertical 2T (V2T) NOR Flash architecture that provides not only scaling capability but also low-power solutions. We leveraged the process of standard 3D NAND to develop a vertical 2T NOR that produces even smaller cell size than conventional planar 1T NOR. Advanced high-K metal-gate (HK/MG) integration is developed to provide high-performance BE-MANOS charge-trapping device with excellent 1M endurance and retention reliability. The 2T NOR architecture provides low-voltage read (~1V) that is compatible with advanced CMOS circuits without charge pumping to save power. We also suggest future technology extensions of the V2T NOR by adopting the ferroelectric memory devices (FeFET) and the 3DIC chiplets integration to broaden the applications fields of NOR technology in embedded Flash and computing in memory (CIM).

We report an extremely scaled HC 3D NAND device with large memory window in this paper. The proposed cell area $(0.009\mu \mathrm{m}^{2}/\mathrm{layer})$ is only ~ 32% of the standard GAA 3D NAND cell area, while it can produce very large $gt; 10\mathrm{V}$ Vt memory window with excellent 100K endurance. We also study the size effect of HC device. It is found that the larger (taller) HC device may easily suffer parasitic edge leakage effect that causes programming saturation issue. A “wake-up” effect by an initial strong -FN erasing can introduce gate injected electrons that electrically suppress the parasitic edge and in turn “wake-up” the device to produce larger programming window. On the other hand, the smaller HC device already shows excellent memory window without the need of wake-up. Good post-cycled retention and RTN performance are demonstrated for an extremely scaled, “hero” HC device. Our results suggest a promising path of 3D NAND device to enjoy both aggressive dimension scaling and large memory window.

Deep neural networks (DNNs) are very popular these years owing to their powerful capability in many artificial intelligence (AI) applications of classification and recognition. The computing-in-memory (CIM) is an emerging method that utilizes memory arrays directly as the computing units to accelerate the DNN calculation. Different from the conventional Von Neumann architecture, CIM can drastically reduce data movements and power consumption. An optimal method was proposed to transform 3D NAND Flash into a high-bandwidth, high-density and low-power nonvolatile CIM (nvCIM) [1]. In this paper, we further analyze the read disturb of 3D NAND Flash nvCIM based on a previous study [2]. The simulation results indicate that the optimized 3D NAND device is able to sustain sufficient inference accuracy over 10G read stress which may support up to 10-year usage for applications on edge DNN computing.

In this paper, we introduce the optimal design methods of 3D NAND nvCIM [1], and then address the read disturb reliability issue. In recent years CIM [2] is widely considered as a promising solution to accelerate the DNN inference hardware. Theoretically, nvCIM can drastically reduce the power consumption by data movement because of no need to move the weights during computation. 3D NAND has the advantage of extremely low Icell (~nA), while the large ON/OFF ratio provides the capability to sum >10’000 cells together to improve the performance bandwidth and energy efficiency. We think that 3D NAND nvCIM has the potential to serve as the inference accelerator for the high-density fully- connected (FC) network which often requires high-bandwidth inputs. The read disturb property is studied. It is suggested that the "on-the-fly" calibration technique can well maintain the inference accuracy for 10-year usage.

We propose optimal design methods of 3D NAND Flash to achieve high-density, high-bandwidth and low-power nvCIM. By suitably engineering the device, we can produce ultra-low ON current of 2nA (mean) at saturated region instead of subthreshold region, while the OFF leakage current is much below 1pA. Such low Ion and large ON/OFF ratio provide large bandwidth to parallelly sum more than 10’000 cells together to offer high efficiency for DNN computing. The three-dimensional summation in 3D NAND also allows effective multi-bit resolution of weight without resorting to complex analog memory design. For the first time we witnessed the power of "central limit theory" in 3D NAND nvCIM, where the large number of summation averages out the noise and provides high accuracy of MAC. The effect of non-ideal cell variations, noises and shifts are studied systematically. Through adequate calibration techniques the 3D NAND nvCIM can provide accuracy close to the software limitation, with reasonable tolerance to various device errors. The 3D NAND nvCIM is promising to be an energy-efficient (TOPS/W~40) edge computing solution for large neural networks (>100Mb weight).

A novel hemi-cylindrical (HC) 3D NAND Flash architecture is demonstrated for the first time. HC 3D NAND squeezes the gate-all-around (GAA) hole in one direction, followed by a slit cut to split the GAA device to produce twin cells. It creates ~ 2.6 times of memory density increase than standard GAA 3D NAND at the same stacking layer. Both experimental and simulation results clarify that the "non-local" effect of channel potential can essentially "smooth" the non-uniform curvature effect thus the HC 3D NAND device possesses regular P/E window characteristics even it is not a regular shape of GAA. Good 100K PE cycling endurance and post 10K-cycled 150C retention are demonstrated. HC 3D NAND structure has potential to further scale 3D NAND device in lateral dimension, with the advances of processing technologies.

For the first time, we experimentally demonstrate an FET with a polycrystalline silicon (poly-Si) device featuring supersteep subthreshold slope (SS) around 20 mV/decade at room temperature. This novel dual-channel device is a three-wordline (WL) transistor fabricated in a poly-Si channel, with p+ source and n+ drain. The outer two WLs serve as the pass gates that control the virtual junction of the center WL device (main gate). Whether n-channel or p-channel characteristics are achieved depend on the bias polarity applied to the pass gates. Both read modes exhibit supersteep SS behavior for the center main gate. Theoretical analysis suggests that this three-WL FET device creates a gate-controlled thyristor mode, where a positive feedback current is induced when the center main gate voltage is above the onset value to induce the turned-on thyristor. Different from the usual tunneling FET (with reverse-biased junction bias), the p+/n+ junction is forward biased, and thus, the read current can approach $10~\mu \text{A}$ even for a narrow-width (~32 nm) poly-Si thin-film transistor, amounting to 0.3-mA/ $\mu \text{m}$ drive current. This device displays no hysteresis between forward and reverse voltage sweeping, and the steep SS has weak temperature/size dependence.

The advantage of using extremely-thin body (ETB, Tsi=3nm) device has been demonstrated in a 3D NAND Flash test chip. Net P/E memory window gain of >1.3V is observed for devices using ETB poly-Si. This substantial gain can be explained by the “quantum confinement” that raises effective Si bandgap and in turn reduces the tunneling barrier height. Simulation model has been validated and it shows equivalent barrier height reduction of ~0.16eV and 0.07eV for electron and hole, respectively for Tsi=3nm. Meanwhile, the extremely-thin body poly silicon channel can improve S.S. to nearly 250mV/dec, which is close to bulk 2D Flash devices. However, the Idsat is degraded to only 160nA for Tsi=3nm, which is attributed to the larger effective mass or higher contact resistance. The degraded Idsat can be accommodated by lower Isense

A self-healing Flash with micro heater was proposed [1] to enable very high endurance (100M) for NAND Flash device by heating the device locally during P/E cycling stress. In this work, we propose to use the self-healing 3D NAND Flash with thermal assisted programming/erasing speed and much higher endurance to improve the performances of fast SLC NAND in NVDIMM applications. By applying an in-situly thermal heating of nearly 600C during programming and erasing we demonstrated the feasibility of sub-usec thermal assisted programming, and sub-10usec thermal assisted erasing with 100M endurance for SLC operation. The retention of self-healing 3D NAND Flash after 100M endurance still remains well, suggesting the good healing effect. System-level simulations indicate much reduced latency by the boosted PGM/ERS, while the greatly improved endurance greatly reduces the need for spare blocks for wear leveling (=lower cost) for NVDIMM applications.

The coming era of artificial intelligence (AI) and the combination with internet of things (IoT) will require a large number of edge computing inference devices. We consider 3D NAND Flash has great potential to provide either near-memory or in-memory computing for low-cost high-performance inference device. One of the critical technology challenge of 3D NAND Flash for inference application is the read disturb, because in this application the NAND Flash needs to sustain continuous read over the entire product life time. In this work, we have studied how to optimize read disturb performance of single-gate vertical channel (SGVC) 3D NAND and demonstrated the possibility to meet > 10T (1E13) continuous read which may exceed 10-year usage without the need of data refresh.

In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage ( $V_{t}$ ) shift due to two unique mechanisms. The first mechanism is the fringing field of the programmed charges (Z-interference), whereas the second one is the degraded inhibited potential affected by the programmed PL channel, which is grounded (Z-disturbance). Z-interference happens before Z-disturbance, so it is more critical to the memory window. Optimizing PL/OX thickness or engineering the PL sidewall profile can balance the constraint of Z-interference and the demand of higher memory density. They are important guidelines when designing VG-type 3-D NAND memory.

We introduce a novel 3D AND-type NVM suitable for in-memory computing for AI applications. The structure resembles our SGVC 3D NAND, but we introduce a vertical buried diffusion (BD) line that connects all transistors in parallel in the same trench of a 3D AND-type array. The 3D AND-type array readily enables the summation of currents from plural BL’s (or WL’s) to provide "vector matrix multiplications", or often called "MAC" in AI. Because all the weights are stored in the high-density NVM and current sensing of memory cells already provides MAC operation, the in-memory computing with NVM provides a way to eliminate the need of moving data from DRAM and SRAM through buses or chip I/Os, thus this is ideal for AI computing. This device has potential to provide high-density, low-power, and high-throughput hardware solutions to accelerate the AI computing.

An AND-type stackable 3D NVM architecture is proposed to provide an ultra-high density AI computing memory with low power. The advantages are: (1) All memory transistors in the 3D array are connected in parallel, thus enable the sum-of-product operation. (2) The 3D NAND like architecture is possible to stack to > 64 layers, thus provides ultra-high density (>128Gb) AI memory. (3) Many bit lines (>1KB) can operate in parallel for high bandwidth. (4) Uses low-power +/− FN programming/erasing which allows high parallelism, and is bit-alterable thus is ideal for training or transfer learning. (5) Excellent linearity of output current with respect to bitline bias, thus enabling ideal analog computation. (6) Adequate sensing current of the summed product thus permits fast access read for inference device. The proposed memory architecture can achieve TOPS/W>10, which is 10X greater than the conventional von Neumann architecture.

A novel dual-channel 3D NAND device was proposed previously [1]. In addition to the N- and P-channel read operations, such device can also perform a special "thyristor mode" which possesses super steep subthreshold slope (S.S. ~0). In this work, we studied 4 different types of read methods with the same device, which are normal N- and P-channel read, and thyristor-mode N- and P-channel read, respectively. These 4 different read methods can be carried out by just simply changing the bias arrangements of wordlines so that the IdVg curves can behave differently. An interesting finding is that the Vt window of P/E cycling and retention are quite different among these sensing methods. It may provide a new methodology to understand the charge storage mechanisms. This work provides a comprehensive study for understanding the operation physics of this novel device.

The charge-trapping devices used in 3D NAND Flash often possess certain fast initial charge loss behaviors, leading to degraded programming distributions. A possible design method to improve the programming distribution is to insert an additional programming phase named as "counter-pulse" (CP), which is applied immediately after +FN programming but just before the program verify (PV). Such CP programming method is verified to be very useful to tighten the PV distribution for better memory window. In this work, CP programming method is studied extensively in order to optimize the memory window and programming performance for a SGVC 3D NAND Flash product chip.