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1. Perspectives on Backside Power (PowerVia)

3. A multi-country analysis of COVID-19 hospitalizations by vaccination status

4. Correction: Epidemiology and outcomes of early-onset AKI in COVID-19-related ARDS in comparison with non-COVID-19-related ARDS: insights from two prospective global cohort studies (Critical Care, (2023), 27, 1, (3), 10.1186/s13054-022-04294-5)

5. Smartphone Addiction among Syrian Medical Students

7. E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology

8. Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing

9. Syrians' awareness of cardiovascular disease risk factors and warning indicators : a descriptive cross-sectional study

10. Monkeypox in Syria : Highlighting an awareness issue

11. NHANES cross sectional study of aspirin and fractures in the elderly

13. Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

14. GaN and Si Transistors on 300mm Si(111) Enabled by 3D Monolithic Heterogeneous Integration

16. Transistor reliability characterization and comparisons for a 14 nm tri-gate technology optimized for System-on-Chip and foundry platforms

17. A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products

18. A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

20. RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

21. A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

23. A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

24. A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

25. A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications

26. A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

41. VERTICAL SCALING OF TYPE I InP HBT WITH FT > 500 GHZ.

44. Lateral scaling of 0.25 µm InP/InGaAs SHBTs with InAs emitter cap.

45. Record f[subT] and f[subT] + [supf]MAX performance of InP InGaAs single heterojunction bipolar transistors.

48. A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products.

49. InP/InGaAs SHBTs with 75 nm collector and f[subT] >500 GHz.

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