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We present an experimental study optimizing a band-engineered gate-stack by incorporating both a tunnel dielectric layer (TDL) and a gate blocking layer (GBL) for ferroelectric (FE) nand flash applications, with a total thickness budget of 18 nm. Using Hf $_{{0}.{5}}$ Zr $_{{0}.{5}}$ O2 (HZO) as the FE material, we explore Al2O3, SiO2, Si3N4, and HfO2 as TDL and GBL materials. By systematically varying the location and thickness of each layer, we investigate their impact on memory window (MW) performance. Our results show that material choice and positioning within the gate-stack are critical, even with constant overall thickness. A hybrid stack using 2-nm Al2O3 and 4-nm SiO2 as TDL and GBL, respectively, results in a maximum MW of 11 V. When Al2O3 and SiO2 are positioned as GBL above the HZO layer, the MW is slightly reduced (>7.5 V), with an increased tetragonal phase. Conversely, MW is significantly reduced when Al2O3 and SiO2 are used as GBL and TDL, respectively, or when both are used as TDL. Further exploration using SiO2, Si3N4, and HfO2 as TDL materials with an SiO2 GBL shows that HfO2 and SiO2 as TDL lead to quad-level cell (QLC)-compatible MW, whereas Si3N4 as TDL leads to very low MW. HfO2 as TDL material leads to most optimized gate-stack with QLC compatibility and lowest operating voltage of all materials. This study underscores the importance of dielectric (DE) material selection and layer positioning within the gate-stack in optimizing the MW of hybrid gate-stacks.

We study the disturb characteristics of ferroelectric field-effect transistors (FEFETs) with band-engineered gate stacks. We demonstrate that integrating a dielectric Al2O3 layer within the ferroelectric (FE) Hf $_{{0}.{5}}$ Zr $_{{0}.{5}}$ O2 layer in the gate stack significantly enhances the memory window (MW), achieving levels suitable for quad-level cell operation (approximately 7.5 V) while operating at a reduced write voltage (below 15 V). Despite these improvements, the band-engineered FEFET exhibits similar pass disturb characteristics in the PGM state as a standard FEFET with an FE-only gate stack. To improve the disturb characteristics, we introduce and validate a periodic refresh-based disturb mitigation scheme, analogous to strategies employed in SSD controllers and flash memory managers for traditional charge trap flash-based NAND chips. This mitigation scheme reduces disturb in the PGM state from ~28% to approximately ~4% in the band-engineered FEFETs, enabling large memory window, low-disturb operation.

In this work, we report atomic-layer-deposited (ALD) based all-oxide transistors toward vertically stacked high-density logic and memory for 3-D integration. This structure utilizes thick degenerated ALD In2O3 as the conducting gate, and ALD In2O3 thin film itself serves as source/drain contacts to the ALD In2O3 channel without metal contacts and gate formation. The all-oxide field-effect transistors (AOFETs) not only survived under high-temperature annealing over $400~^{\circ }$ C but also gained a boosted on-/off-ratio over $10^{{7}}$ with subthreshold swing (SS) close to 60 mV/dec at room temperature. AOFETs present high uniformity and very robust reliability with a threshold voltage instability ( $\boldsymbol {\Delta } {V}_{\text {TH}}\text {)}$ of −5 and −50 mV under positive bias stress (PBS) and negative bias stress (NBS) tests for $10^{{4}}$ s. The vertical AOFETs (V-AOFETs) demonstrate good gate modulation from sidewall In2O3 with thickness as well as gate length ( ${T}_{\text {IO,{g}}}\text {)}$ of 10 nm, achieving on-/off-ratio over $10^{{5}}$ and maximum current ( ${I}_{\max }\text {)}$ over $160~\boldsymbol {\mu } $ A/ $\boldsymbol {\mu } $ m. Vertical all-oxide ferroelectric FETs (V-AO-FeFETs) show a memory window (MW) of 1.85 V, with endurance and retention extended to $10^{{12}}$ cycles and ten years at room temperature, respectively. These findings illustrate that the vertical-channel all-oxide devices based on ALD oxide semiconductors (OS) are promising candidates for future high-density logic and memory applications in 3-D integration.

Multibridge channel-ferroelectric field-effect transistor (MBC-FeFET) with metal-ferroelectric-metal-insulator-silicon (MFMIS) gate-stack is an advanced noble memory device, which is compatible with a 3-nm node technology logic device. Thanks to the wide effective channel width of the device’s stacked nanosheet (NS), the capacitance ratio of the interfacial layer (IL) and ferroelectric layer ( ${C}_{\text {IL}}$ / ${C}_{\text {FE}}$ ) can be maximized without area penalty, significantly improving memory window (MW) and endurance characteristics. In this work, we developed analytical compact models of memory characteristics for MFMIS gate-stack-based MBC-FeFET. Also, using this model, the gate-stack design guidelines were presented. As a result, the MW becomes three times larger, and the electric field in the IL layer ( ${E}_{\text {IL}}$ ) becomes 0.17 times smaller after optimization. This is 21 times larger MW compared to a planar FeFET with initial gate-stack parameters applied.

Herein, applying a multiscale approach that combines technology computer-aided design (TCAD) simulations and ab initio calculations, we investigate the electronic and transport properties of the titanium nitride (TiN) - indium-gallium-zinc oxide (IGZO) Schottky contact. We first carry out the machine learning-assisted TCAD calibrations for the measurement data obtained from the IGZO-based FET, achieving over 90% consistency in terms of electrical test characteristic as well as the specific contact resistivity. In particular, we point out that the high Schottky barrier height at the TiN-IGZO contact is obtained from the machine learning-based parameter optimization. To identify the electric origin of the high Schottky barrier height, we next perform the density functional theory calculations. We initially identify the oxidative stability of the TiN-IGZO contacts and reveal that the formation of the titanium oxide (TiO $_{\text {x}}\text {)}$ at the interface is energetically favorable. Adopting the TiN-TiOx-IGZO contact atomic structures, we study their transport properties and unravel that the high Schottky barrier height originates from the interface dipole at the TiN-TiOx contact. The microscopic understanding obtained in this study will provide design guidelines for the development of next-generation DRAM devices.

In ferroelectric FETs (FeFETs), the transient characteristics is a key issue to be addressed. Therefore, it is important to have an understanding based on accurate measurements of transient characteristics. In this work, the in-situ threshold voltage (Vt) measurement method is presented, which allows simultaneous observation of the change of remnant polarization (Pr) and Vt over delay time within a device. This provides insight into the characteristics of both Pr and trapped charge depending on delay time (tdelay). The transient characteristic after applying the positive voltage is particularly important, as electrons are injected from the channel side. Thus, we show that the time to a steady state of program Vt is shortened by controlling the electrons by applying a small negative voltage immediately after the positive voltage.

In this work, with the goal of developing a large memory window (MW) ferroelectric field-effect transistor (FeFET) for high-density stand-alone storage applications, we provide a deep look into the MW of a FeFET and clarify the definition on the MW through combined theoretical and experimental studies. We show that the following hold: 1) conventionally thought maximum MW of a FeFET (i.e., $2{E} {_{\text {C}}} {t} {_{\text {FE}}}$ ) is accurate only for dc sweep and may not be accurate for pulsed memory operation as it neglects the contribution from other layers in the gate-stack; 2) for intrinsic FeFET operation that only depends on polarization switching, adding a dielectric layer into a FeFET gate-stack at best keeps the same MW as the one without the dielectric layer if assuming the same polarization is switched in both cases or worse as most likely less polarization can be switched; 3) by integrating FeFETs with or without a top dielectric Al2O3 layer, we demonstrate from experiment that adding a dielectric layer reduces the MW; and 4) with a 20-nm-thick HfO2, a large MW of 4.8 V is demonstrated, which can accommodate tightly distributed multilevel cell (MLC) and triple-level cell (TLC), showing the potential of FeFET as high-density storage technology.

In this work, we have developed a large memory window (MW) ferroelectric field effect transistor (FeFET) memory for vertical NAND storage. We demonstrate that: 1) by inserting a top functional layer above the ferroelectric, gate side injection pumped by ferroelectric switching event can be enhanced, thus increasing the MW; 2) inspired by the charge trap flash, SiNX is chosen as the charge trapping layer and the proposed structures have been experimentally demonstrated to effectively increase MW; 3) the MIFIS structure demonstrates a 6V-8V MW for 11V $1\boldsymbol {\mu } $ s write pulse and 8V-12V window for 15V $1\boldsymbol {\mu } $ s with a SiOX composite functional layer; 4) interestingly, the MIFIS device shows immediate read-after-write capability, which is not observed in the baseline FeFET, suggesting minor channel side injection and relaxation.

Basic gate stack structure of the Ferroelectric FET is Metal-ferroelectric-insulator-silicon (MFIS), where the memory window (M.W) is $2^{\ast } $ (Pr-Q $_{\text {it}}\text {)}$ /CFE considering the trapped charge. However, in Metal - insulator - ferroelectric - insulator - silicon (MIFIS) gate-stacked FeFETs, the M.W is $2^{\ast } $ {(Pr-Q $_{\text {it}}\text {)}$ /C $_{\text {FE}} +$ (Q’it-Q $_{\text {it}}\text {)}$ /C $_{\text {G. {IL}}}\text {)}$ }, which allows the M.W to widen in case the Q’it injected from the gate side is larger than the Qit injected from the channel side. In this letter, we propose a band engineered (BE) gate insulator in MIFIS gate-stacked FeFETs. This lowers the energy barrier of the hole when applying the program voltage, thereby increasing the amount of hole injected from the gate side, and consequently widening the M.W. Furthermore, it is demonstrated by TCAD simulation that the physical origins of Vt shift of PGM state is hole injection. In addition, in the case of BE-MIFIS gate-stacked FeFETs, the maximum ISPP slope is increased by about 2 times compared to conventional MIFIS, which is an important feature in ferroelectric VNAND (FeVNAND) operated at low voltage.

Beyond MBCFETTMtechnology, the 3-dimensional stacked FET (3DSFET) emerges as a promising contender, featuring a structure that stacks NMOS and PMOS vertically to continue area scaling and improving the energy efficiency of logic technology. In this study, we report successful CMOS operations of 3DSFET by implementing vertical integration of a Source/Drain (SD), metal gate, and contacts including Self-Aligned Direct Backside Contact (SA-DBC) in an industry-compatible Contacted Poly Pitch (CPP) of 48 nm.

This paper reviews key memory technologies for sub-40 nm node. Physical challenges to shrink the technology are addressed for DRAM, NAND Flash, and PRAM, and potential solutions are discussed in terms of materials, processes and device structures. It is believed that DRAM can scale down to at least 30 nm node with the aid of novel capacitor materials and 3-dimentional cell transistors, and NAND Flash can scale down to at least 30 nm node with the help of high-k dielectrics and novel cell structures. PRAM will create a new market with its new functionality in near future.