Optimizing Memory Window for Ferroelectric Nand Applications: An Experimental Study on Dielectric Material Selection and Layer Positioning

We present an experimental study optimizing a band-engineered gate-stack by incorporating both a tunnel dielectric layer (TDL) and a gate blocking layer (GBL) for ferroelectric (FE) nand flash applications, with a total thickness budget of 18 nm. Using Hf<inline-formula> <tex-math notation="LaTeX">$_{{0}.{5}}$ </tex-math></inline-formula>Zr<inline-formula> <tex-math notation="LaTeX">$_{{0}.{5}}$ </tex-math></inline-formula>O2 (HZO) as the FE material, we explore Al2O3, SiO2, Si3N4, and HfO2 as TDL and GBL materials. By systematically varying the location and thickness of each layer, we investigate their impact on memory window (MW) performance. Our results show that material choice and positioning within the gate-stack are critical, even with constant overall thickness. A hybrid stack using 2-nm Al2O3 and 4-nm SiO2 as TDL and GBL, respectively, results in a maximum MW of 11 V. When Al2O3 and SiO2 are positioned as GBL above the HZO layer, the MW is slightly reduced (>7.5 V), with an increased tetragonal phase. Conversely, MW is significantly reduced when Al2O3 and SiO2 are used as GBL and TDL, respectively, or when both are used as TDL. Further exploration using SiO2, Si3N4, and HfO2 as TDL materials with an SiO2 GBL shows that HfO2 and SiO2 as TDL lead to quad-level cell (QLC)-compatible MW, whereas Si3N4 as TDL leads to very low MW. HfO2 as TDL material leads to most optimized gate-stack with QLC compatibility and lowest operating voltage of all materials. This study underscores the importance of dielectric (DE) material selection and layer positioning within the gate-stack in optimizing the MW of hybrid gate-stacks.