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173 results on '"HAUSER, J.R."'

1. Diagnostic Microbiology

Author

Cintrón, M., primary, Hauser, J.R., additional, Otto, C., additional, Persing, D.H., additional, and Tang, Yiwei, additional

Published
2019
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2. Mobility behavior of n-channel and p-channel MOSFET's with oxynitride gate dielectrics formed by low-pressure rapid thermal chemical vapor deposition

Author

Vogel, Eric M., Hill, Winford L., Misra, Veena, McLarty, Peter K., Wortman, Jimmie J., Hauser, J.R., Morfouli, P., Ghibaudo, Gerard, and Ouisse, T.

Subjects
Metal oxide semiconductor field effect transistors -- Research, Electron mobility -- Observations, Gates (Electronics) -- Usage, Chemical vapor deposition -- Usage, Business, Electronics, Electronics and electrical industries
Abstract

The mobility behavior of MOSFET's with oxynitride gate dielectrics results from traps in the films. Gate dielectric fabrication involves the use of low-pressure rapid thermal chemical vapor deposition with SiH4, N2O, and NH3. An increase in nitrogen and hydrogen concentration reduces the peak electron mobility in n- and p-channel MOSFET's. Hole mobility decreases for all electric fields.

Published
1996

3. Vertically scaled MOSFET gate stacks and junctions: how far are we likely to go?

Author

Osburn, C.M., Kim, I., Han, S.K., De, I., Yee, K.F., Gannavaram, S., Lee, S.J., Lee, C.-H., Luo, Z.J., Zhu, W., Hauser, J.R., Kwong, D.-L., Lucovsky, G., Ma, T.P., and Ozturk, M.C.

Subjects
Metal oxide semiconductor field effect transistors -- Research, Gates (Electronics) -- Research, Semiconductors -- Junctions
Abstract

The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure Si[O.sub.2] in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equivalent oxide thickness (EOT)--for example, Hf[O.sub.2], Zr[O.sub.2], and their silicates. Nevertheless, considerable challenges lie ahead if we are to achieve an EOT of less than 0.5 nm. If only a single molecular interface layer of oxide is needed to preserve high channel mobility, it seems likely that an EOT of 0.4-0.5 nm would represent the physical limit of dielectric scaling, but even then with a very high leakage (~[10.sup.5] A/[cm.sup.2]). For junctions, the main challenge lies in providing low parasitic series resistance as depths are scaled in order to reduce short-channel effects. Because contacts are ultimately expected to dominate the parasitic resistance, low-barrier-height contacts and/or very heavily doped junctions will be required. While ion implantation and annealing processes can certainly be extended to meet the junction-depth and series-resistance requirements for additional generations, alternative low-temperature deposition processes that produce either metastably or extraordinarily activated, abruptly doped regions seem better suited to solve the contact resistance problem.

Published
2002

4. An evaluation of super-steep-retrograde channel doping for deep-submicron MOSFET applications

Author

Tian, H., Hulfachor, R.B., Ellis-Monaghan, J.J., Kim, K.W., Littlejohn, M.A., Hauser, J.R., and Masnari, N.A.

Subjects
Metal oxide semiconductor field effect transistors -- Research, Semiconductor doping -- Research, Business, Electronics, Electronics and electrical industries
Abstract

Self-consistent Monte Carlo and drift-diffusion simulation studies help analyze the performance increase and degradation of deep-submicron super-step-retrograde (SSR) channel doped MOSFETs (metal oxide semiconductor field-effect transistors). SSR channel doped MOSFETs show higher current drive and lower threshold voltage compared to conventional MOSFET structures. Hot carrier effects and high junction capacitances limit the performance of SSR channel doped MOSFET mechanism. Design trade-offs for deep-submicron SSR MOSFETs are studied.

Published
1994

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