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Radio frequency (RF) micro-electro-mechanical systems (MEMS) capacitive switches show great promise for use in wireless communication devices such as mobile phones, but for the successful application of these switches their reliability needs to be demonstrated. One of the main factors that limits the reliability is charge injection in the dielectric layer (SiN) which can cause irreversible stiction of the moving part of the switch. We present a way to characterize charge injection. By stressing the dielectric with electric fields on the order of 1 MV/cm, we inject charge in the dielectric and measure the effects it has on the CV curve. Instead of conventionally measuring the change of the pull-in voltage, the presented center shift method measures the change of the voltage at which the capacitance is minimal. This way, the measurement method does not influence the charge injected by the stress voltage. Another advantage is that the measurement of the amount of injected charge is not influenced by changes in the width of the CV curve. These two advantages make it possible to test RF-MEMS capacitive switches in a more accurate way.

Transient enhanced diffusion of boron marker layers following silicon ion implantation shows a complex behavior as a function of annealing temperature and time. In the initial phase of ripening, small clusters with low binding energy give rise to an extremely large interstitial supersaturation (∼106–107 at 600°C). As the clusters ripen into {113} defects the supersaturation drops to a level which remains almost constant with time until the {113} defects have dissolved. By inverse modeling of the Ostwald ripening process, values are extracted for several basic physical parameters: the energy barrier for boron-interstitial association, the dissociation energy Ediss of the migrating boron-interstitial species, and the interstitial self-diffusion product. The data are consistent with recent ab initio predictions that the migrating boron species is a boron-interstitial pair. Analysis of the detailed time evolution of TED allows us to extract Ediss for silicon clusters and {113} defects as a function of defect size, n. We find strong oscillations on Ediss in the size range 2

The transient supersaturation in a system undergoing Ostwald ripening is related to the cluster formation energy ${E}_{\mathrm{fc}}$ as a function of cluster size $n$. We use this relation to study the energetics of self-interstitial clusters in Si. Measurements of transient enhanced diffusion of B in Si-implanted Si are used to determine $S(t)$, and inverse modeling is used to derive ${E}_{\mathrm{fc}}(n)$. For clusters with $ng15$, ${E}_{\mathrm{fc}}\ensuremath{\approx}0.8\mathrm{eV}$, close to the fault energy of ${113}$ defects. For clusters with $nl10$, ${E}_{\mathrm{fc}}$ is typically 0.5 eV higher, but stabler clusters exist at $n\ensuremath{\approx}4$ ( ${E}_{\mathrm{fc}}\ensuremath{\approx}1.0\mathrm{eV}$) and $n\ensuremath{\approx}8$ ( ${E}_{\mathrm{fc}}\ensuremath{\approx}0.6\mathrm{eV}$).

The increasing complexity of modern technologies has made semiconductor process and device development challenging. A reduction in the number of experimental tests and a detailed internal insight opens the way to a more optimized process in a shorter time at reduced costs and development time. This has largely increased the use of virtual technology platforms for technology development and circuit optimization in e.g. RF BiCMOS applications. The capability of accurate predictions and directly linking basic technology parameters to RF circuit performance makes virtual technology a very powerful tool during RF process and device development. Commercially available technology computer-aided design (TCAD) tools are generally used during device fabrication and characterization, process optimization, and circuit design. With three examples we illustrate the evolution of the virtual technology process used for RF BiCMOS development within NXP Semiconductors. In the first two examples, we illustrate device and process optimization while in the third example we describe a new way of combining device and process optimization with circuit simulations by means of a distributed equivalent circuit. It allows to take the interaction between the intrinsic device (i.e. device doping profile) and the parasitic environment (i.e. device architecture) efficiently into account for high-frequency applications and in particular for low-noise circuits.

RF MEMS capacitive switches show great promise for use in wireless communication devices such as mobile phones, but the successful application of these switches is hindered by reliability concerns: charge injection in the dielectric layer (SiN) can cause irreversible stiction of the moving part of the switch. We present a new way to characterize charge injection. By stressing the dielectric with electric fields on the order of 1 MV/cm, we inject charge in the dielectric, and use a new method to measure the effects it has on the C-V curve. Instead of measuring the change in the pull-in voltage, this method measures the change in the voltage at which the capacitance is minimal. This way, no extra charge is injected during the measurement of the amount of injected charge, which reduces the effect it has on the tested switches, so that the effect of the intentionally induced stress voltage is not obscured by the measurement method.

This paper reports on the power performance of RF high-breakdown voltage (>16.5 V) SiGeC HBT power devices, which have been successfully integrated into a BiCMOS platform featuring 0.25 /spl mu/m CMOS and a full set of high-quality passives. These devices have an excellent tradeoff between power gain and breakdown voltage. The high speed combined with low parasitic elements enables over 80% power-added efficiency (PAE) and corresponding power gains (G/sub p/) of 18 dB and higher over a relatively wide range of power densities. A peak performance of 88% PAE and 20 dB G/sub p/ is obtained at 0.25 W continuous-wave output power with a 792 /spl mu/m emitter length device (396 /spl mu/m/sup 2/ emitter area) operating at 1.8 GHz with 3.3 V supply voltage. Excellent power scaling versus emitter area is obtained. Measured output power shows an ideal increase of 3 dB when doubling the area. Also the corresponding matching scales. This is achieved by minimizing parasitic elements using deep trench isolation and careful design of the metal wiring. Furthermore, the base and emitter doping profiles are tuned to minimize the temperature dependence of the power gain. In combination with the high PAE, no effect of self-heating on power scaling is found.

We study the influence of parasitic series resistances on the cut-off frequency of high-speed SiGe hetero-junction bipolar transistors. Due to coupling of the parasitic resistances with the internal collector-base capacitance, significant extra delay time is introduced. This extra delay will cause saturation, or even a decrease of f/sub T/ at higher collector doping levels. In addition, we study the optimisation of an n-cap emitter profile, which is only possible when the collector delay is reduced to a minimum, and the series resistances are properly included.

SiGe is widely used in high-frequency bipolar transistors because of its low bandgap and compatibility with silicon. Here we exploit the same benefits of SiGe in a new application area, namely ultrafast power rectifiers. We have produced discrete p/sup +/(SiGe)-n/sup -/n/sup ++/ diodes with low forward voltage drop, low stored charge, and a soft recovery. The performance far exceeds that of conventional devices. These improvements are achieved without resorting to lifetime killing and thus the devices can be easily integrated into power ICs.

Npn-type SiGe heterojunction bipolar transistors (HBT's) have high cut-off frequencies, but low breakdown voltages due to their high current gain. We show that a SiGe layer in the emitter can increase the base current and hence the breakdown voltage while the collector current and cut-off frequency are not reduced. Simulations and first experimental results clearly confirm this effect.

Double-polysilicon bipolar junction transistors with an ultra shallow implanted base are fabricated using Ge pre-amorphization. The effect of implanted C, both on suppressing transient enhanced diffusion and on the junction leakage, is studied.

Test devices with collector doping and thickness variations have been made to investigate conventional double poly bipolar junction transistors (BJTs) for use in RF power amplifiers at supply voltages down to 2 V. Measurements and simulations have been performed on power efficiency, gain and linearity. It has been found that efficiencies saturate at about 62-65% (at 1.8 GHz) for thin collectors. From comparison with harmonic balance simulations, this effect is explained by observing that efficiency is limited by hard saturation (which is the same for all devices presented in this paper) rather than by the current and gain limiting "quasi-saturation" effect which dominates in devices with thicker epilayers. Two-tone intermodulation measurements indicate that BJTs are suitable for use in handsets based on e.g. Enhanced Datarate for GSM Evolution (EDGE).

The power added efficiency (PAE) of low voltage RF bipolar power transistors for cellular applications, is carefully analyzed experimentally and theoretically. We found that the transistor with low output capacitance operates in "inverse class AB", which facilitates high efficiencies. FE as high as 77% at 1.8 GHz with 3.5 V supply voltage have been obtained.

For the first time, we show an enhanced RF power gain by eliminating the emitter bondwire inductance in emitter plug grounded mounted bipolar transistors. By grounding the emitter with a substrate contact to a low-ohmic substrate, the emitter bondwire is effectively short-circuited. At maximum output power, 0.5 W with a power added efficiency >60%, an increase in power gain of 2 dB, up to 14.5 dB, is observed. For 0.2 W output power, an increase of 5 dB, up to 19 dB, is observed.

A-BCD is a family of 100 V BCD processes on SOI offering latchup free operation, improved robustness, superior EMC performance, higher packing density, lower mask count, high temperature and higher frequency operation and easier design over bulk silicon technology. A wide range of a passive and active (5/12/25/60 and 100 V) devices are available. Device design tradeoffs for n- and p-type LDMOS and extended drain PMOS are discussed in detail. This and the low mask count makes it a versatile process for cost-sensitive consumer and automotive markets.

The ripening of ion-beam generated point defects into extended defects has been investigated in detail. The interstitial supersaturation has been extracted from boron marker-layer diffusion after annealing under non-equilibrium defect conditions. We measured a very high initial supersaturation followed by a decrease over many orders of magnitude with a characteristic “plateau” related to the presence of {113} defects. A continuum inverse model has been used to properly describe the ripening of point defects into clusters and their evolution in the presence of a remote sink, e.g. the surface. It evidences that a nonconservative Ostwald ripening process takes place inside the defect band during the annealing and sustains the interstitial supersaturation. The model reveals moreover an oscillatory behaviour of dissociation energies of the nanometer-sized defects which are responsible for the initial high supersaturation. These defects are believed to be {113} precursors.

Low energy implantation is currently the most promising option for shallow junction formation in the next generations of silicon CMOS technology. Of the dopants that have to be implanted, boron is the most problematic because of its low stopping power (large penetration depth) and its tendency to undergo transient enhanced diffusion and clustering during thermal activation. This paper reports recent advances in our understanding of low energy B implants in crystalline silicon. In general, satisfactory source-drain junction depths and sheet resistances are achievable down to 0.18 micron CMOS technology without the need for implantation of molecular species such as BF2. With the help of defect engineering it may be possible to reach smaller device dimensions. However, there are some major surprises in the physical mechanisms involved in implant profile formation, transient enhanced diffusion and electrical activation of these implants, which may influence further progress with this technology. Some initial attempts to understand and model these effects will be described.

Transient enhanced diffusion (TED) and electrical activation (EA) of ion-implanted boron during rapid thermal annealing has been investigated using three types of boron doped p-type Si (100) substrates: (a) Cz 20 Ωcm, (b) 3 μm thick 20 Ωcm epitaxial Si layer (epi-layer) grown on a 20 Ωcm Cz substrate, and (c) 3 μm thick 20 Ωcm epi-layer grown on a 5 mΩcin Fz substrate. The level of oxygen is known to decrease from material type (a) to (c). The samples were implanted with 20 keV, 5×1013cm−2boron and subjected to rapid thermal annealing (RTA) at various temperatures and times. The EA and TED were studied using spreading resistance profiling (SRP) and secondary ion mass spectrometry (SIMS), respectively. Although the amount of TED is almost identical for the three substrates, the EA is found to be significantly higher in the epi-layers compared to Cz substrates. It is speculated that the trapping of vacancies by oxygen in the ion-damaged region leads to an increase in the interstitial supersaturation during annealing, which then results in enhanced boron clustering and reduced electrical activation in the peak of the implanted profile.