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In this paper, two Phase frequency detector (PFD) architectures and a PFD with lock-in detection (PFD-LID) are proposed that are designed using the new techniques for selectively resetting the outputs to achieve improved average gain with a lower blind zone. The two proposed PFDs are designed and fabricated using 180 nm CMOS process. The circuits are tested with the variations in the supply voltage from 1.3 V to 1.8 V, achieving higher average gain and the measured blind zone of 3 ps, which is around five times less than earlier reported works. Also, the proposed selective reset techniques are used to design the PFD-LID. Both the PFDs and PFD-LID are validated using the traditional phase-locked loop (PLL) architecture by achieving minimal settling time of the PLL.

This paper proposes a new architecture for the Phase Frequency Detector (PFD) with improved gain and lower Blind Zone (BZ). The new architecture introduces a selective reset technique with trailing edge detection, which is less sensitive to process and voltage variations in achieving minimal BZ. The proposed PFD is designed and fabricated in 180 nm CMOS process. The circuit is tested for large variations in the supply voltage (1.3 V and 1.8 V), achieving the BZ of 17.5 ps, which is around three times less compared to earlier reported works. The effect of improvement in gain and BZ of the proposed PFD on the reduction of settling time of a phase-locked loop with which the proposed PFD has been integrated is shown with the post-layout simulation results.