A new architecture of the phase frequency detector with improved gain and minimal blind zone for fast settling PLLs

This paper proposes a new architecture for the Phase Frequency Detector (PFD) with improved gain and lower Blind Zone (BZ). The new architecture introduces a selective reset technique with trailing edge detection, which is less sensitive to process and voltage variations in achieving minimal BZ. The proposed PFD is designed and fabricated in 180 nm CMOS process. The circuit is tested for large variations in the supply voltage (1.3 V and 1.8 V), achieving the BZ of 17.5 ps, which is around three times less compared to earlier reported works. The effect of improvement in gain and BZ of the proposed PFD on the reduction of settling time of a phase-locked loop with which the proposed PFD has been integrated is shown with the post-layout simulation results.