Search

When a new technology reaches "mass production", it is not a simple scaling up of the volume. A new set of technical challenges are exposed. These manufacturing excellence challenges are equally important to those achieving record performances during the R&D phase. This paper illustrates "what" and "how" in the manufacturing excellence domain for GaN RF Power technology, especially for achieving ZERO defects.

Lots of studies have been dedicated to NBTI/PBTI in CMOS technologies, where the gate stack is most important. In this paper, we report our study of NBTI/PBTI in LDMOST technologies for RF Power applications. The observed BTI effect is associated to the backend of the processes.

RF Power amplifier often demands Zero-defect in application. However, it sees non-uniform stress during application. The time depend stress level depends on the input signals. This paper presents a way to predict the gate oxide lifetime, not only for the intrinsic oxide breakdown, but also for the extrinsic oxide breakdown. An appropriate gate oxide screening condition would enable the desired quality and reliability level.

With long-life-time of LED lamps, it takes long time to get feedback from field about failure information. We need develop test method, and adopt them in manufacture process to make "early detection" of the failures caused by the variations in component and production process. This paper describe some dominant failures modes we found in market, and some typical tests method used in the manufacturer side to early detection and prevent such failures

A high product reliability means low failure rate. A low failure rate cannot be achieved without manufacturing reliability excellence. With a few concrete examples, this paper illustrates that reliability excellence in SSL manufacturing is needed and can be achieved.

The device architecture and operation conditions of a novel 1.22 µm2 EEPROM cell in 0.18 µm technology node have been revealed. With such a novel cell, the traditional scaling barrier of FLOTOX EEPROM cell has been broken. Reliability aspects of such a cell and the related memory matrix have been extensively studied: the cell endurance. programming and erase disturbs, the stress induced leakage current in the cells, the reliability of sector select gates and the reliability of byte-select gates.

Tail bits appearing during program/erase operation or after retention stresses are major threats to the floating-gate non-volatile memory reliability. Two-transistor (2T)-Fowler–Nordheim (FN)-NOR memories circumvent part of the tail bit induced problems of single transistor NOR and NAND configurations. However, the tail bits still represent a point of concern in the 2T-FN-NOR memory reliability, because of disturbs and stresses induced by application of the inhibition voltage and because of charge retention. In this paper the impact of tail bits in 2T-flash memory is investigated and it is suggested how to tackle this problem from design and process point of view.

Reliability excellence is about meeting customer expectations on reliability. First of all, it is a mind set to achieve excellent product reliability; secondly, it is about identifying the weakest links for reliability improvement and cost saving; and finally act to achieve excellence. An example of LED linear module is given here demonstrating how the principle is applied in practice.

Tail bits appearing during program/erase operation or after retention stresses are major threats to the floating-gate non-volatile memory reliability. Two transistors (2T)-flash architectures circumvent part of the tail bit induced problems of 1T-NOR and NAND configurations. However, the tail bits still represent a point of concern in the 2T-NOR memory reliability, because of the disturbs induced by the application of the inhibition voltage and during the charge retention. In this paper the impact of tails bits in 2T-flash memory is investigated and it is addressed how to face them from the process point of view.

Extensive gate stress measurements after cycling on test structures and on products have been carried out on EEPROMS. The leakage current in the worst case SILC cell has been measured at very low electrical field (down to 1 MV/cm), and has been fitted with various formulae like Fowler-Nordheim (FN), Poole-Frenkel (PF), trap-assisted tunneling (TAT) and hopping conduction model (HCM). In such EEPROMS, a strong asymmetry of SILC has been found. The SILC at low-Vt state is worse than that at high-Vt state. The effect of pulse shaping on suppressing SILC is also demonstrated. A new method is reported to perform data retention estimation and product reliability based on field accelerated tests (gate stress tests). The data retention time of the SILC cell has been determined based on the worst case data from gate stress experiments. The new method can be applied to other floating gate non-volatile memories, such as flash.

Stress-Induced-Leakage-Current (SILC) in sub-half-micron technology embedded EEPROM has been extensively studied by performing gate stress measurements on pre-conditioned EEPROM arrays. This paper reports that the SILC path is very localized; the SILC path can be turned “on” and “off” statistically independent on the electrical field, as shown by the experiments; the SILC caused Vt shift can be fitted into a power-law against the number of programming/erase cycles; the measured current-voltage characteristics of SILC can be well described with Poole-Frenkel model; and EEPROM retention time prediction can be made by extrapolating the gate stress data with fitted Poole-Frenkel parameters.

Solid state lighting (SSL) is widely accepted as the energy efficient technology for general lighting. The market demands in-expensive, long lasting, highly reliable products with high quality of light. At the same time, the product development cycle time is getting shorter and shorter. The reliability professionals are now challenged to perform lifetime assessment for new products that have a much longer lifetime (now typically longer than 50000 operating hours) while the available time to perform such assessment is becoming very short (typically only a few weeks). In addition, these products are not supposed to fail - products with very high reliability are expected.

Many factors (device design, material choice, application conditions, etc.) are determining the reliability of LED light sources. By carefully studying all the key component degradation behavior, and with the thorough knowledge of the LED design, a reliability model can be built here-upon, addressing both the lumen maintenance performances and the probability of catastrophic failures.

Solder joint qualities of light-emitting diodes (LED) lamps have a significant effect on their lifetime. Due to variations in LEDs, the product lifetime is determined by the lowest performing component of the product when multi-LEDs are used. In this paper, we propose a quick electrical inspection method of solder joint quality for LED products, which is obtained by the heating curve measurement for a short time with the forward voltage as a temperature sensitive parameter. The utility of this quick inspection method is verified by the measurement of a solder voids ratio based on the most commonly used approaches in the industry—x-ray. The proposed method is cost effective and only needs around 1–5 s for each LED, which is about one third of the x-ray. Therefore, the quick electrical test method is both meaningful and promising especially when carrying out quality tests on large quantities of solder and can be a highly recommended method to be adopted by the LED lighting industry.

Floating gate cell array reliability associated with high-bit-count per cell (multi-level cell with ≫=3bit/cell) is investigated. A high operating voltage during P/E operation can cause excessive charge injection into the inter-poly-dielectrics layers (IPD), and subsequent charge displacement will cause data retention or read-disturb problems. The Vt shift due to this charge displacement is related to the cell Vt, the amount of trapped charges the nitride layer and the applied external voltage. For a reliable product operation, the high voltage should be limited to keep the charge in the nitride layer to an acceptable level.

In recent years, flash memory has become the driving force in process technology development. This paper discusses a few reliability related effects associated with the scaling of floating-gate based NVM technologies: A) scaling the active area would cause a wider spread of natural Vt of the cells, this brings new challenges in media management and error correction, especially for multi-level applications. B) cell coupling-ratio will reduce due to increasing influence of parasitic capacitances; the inter-cell coupling effect will increase among the neighboring cells; this can affect the cell Vt window or imposes a higher requirement for on chip high voltage handling. C) In embedded memories, a very limited additional thermal budget is allowed on the advanced core logic technology, this brings a new challenge to minimize the thermal budget related to the flash process steps without affecting the flash reliability.

In this paper, we report the program/erase degradation mechanisms in two transistor (2T) Fowler-Nordheim (FN) tunneling operated flash memories, based on extensive experimental study of the degradation characteristics of such 2T-FNFN test memory arrays and reference transistor arrays from several generation process technologies. A quantitative model has been established describing the degradation characteristics under various stress conditions (i.e. degradation due to program/erase cycling at various voltages and temperatures). A software tool has been developed to estimate the reliability performance of various products under different use conditions. This model (and tool) can also be used to estimate the product reliability performance in future process generations.

The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can be determined by studying large flash arrays. Furthermore, the reliability challenges coming along with technology scaling are discussed.

A commonly used method to determine the neutral threshold voltage (Vtn) of floating gate device is by measuring the Vt of the device after a UV erasure treatment. However, such a UV erasure treatment is no more feasible for advanced technologies with Cu backend, because of limited UV transparency of the dielectric stack. A fully electrical method is needed for the determination of such a Vtn. Based on the Fowler-Nordheim (FN) tunneling formula, and by measuring the FN programming and erasure speed characteristics, a perfect straight line can be obtained if I/Eox versus ln(t) is plotted. From the fitting parameters of such a straight line, the Vtn value can be obtained. This method, that is based on the physics of FN tunneling, has been used to derive the neutral threshold voltage (Vtn) of the 90 nm 2T-FNFN embedded flash device before and after P/E cycling. The results give us a good insight in device degradation speed.

The effect of charge displacement in nitride layer of ONO stack in scaled flash cells are experimentally studied by using gate stress measurements. The redistribution of charge is found to follow Poole-Frenkel conduction mechanisms. However, the measurements on scaled devices show significant random telegraph noise. The noise will be even more pronounced in future scaled devices.

Most of the flash endurance results reported so far are typically in a temperature range of -40degC to +85degC, while devices in automotive "under the hood" applications can experience up to 150degC. This paper reports the temperature dependence of FN/FN based flash memories. Experiments have been carried out on 2.7Mb test memory arrays with temperatures up to 150degC. An empirical model has been developed to describe the temperature dependent degradation of the Vt window. This model fits the experimental data over the whole temperature range, and the endurance performance with single shot P/E cycles exceeds 1 million cycles

The bathtub curve is widely used in the reliability world to illustrate three characteristics of the system (or an IC) failure rate curve: the early failure rate during initial phase of life, the intrinsic random constant failure rate in the use life, and the wear-out phase at the end-of-life (Reddy, 2003). The bottom part is usually characterised by a constant failure rate expressed in FIT (failure in time, which is 1 failure in 109 device hours). As systems become more and more complex, more and more redundancy and EDAC (error detection and correction, also called error correction code ECC) are implemented in order to improve the system robustness and reliability (Slayman, 2003 and Ziegler and Puchner, 2004). By studying the data retention failure rates of Flash products with ECC, we found that the bottom part of the bathtub (used to be characterized by "random constant failure rate") is not flat. We suggest replace the FIT number by a cumulative failure fraction with a certain time stamp.

Bake enhanced degradation of gate disturbance of flash cells has been studied. It is found that the worst-case situation exists when the cells are baked in the erased state. The number of cells appearing in the tail distribution can be three times as high when the cells are baked in the erased state than those cells baked in the programmed state. This bake state dependent gate stress behavior can be related to process induced mobile ions or to positive centers in the tunnel oxide.

"New" reliability issues can arise when integrating high-voltage CMOS onto an advanced CMOS technology platform. This papers discusses several issues, like the high-voltage gate oxide integrity, the transistor reliability and the low-k dielectrics in the back-end of the process, with the high voltage application kept in mind. Possible means of improvement are also discussed in this paper.

A new fast wafer level SILC monitoring method, based on parallel floating gate cells, is reported here. The measurement is straightforward, and the stress measurement is not time consuming. It consists of bi-directional FN tunneling stress (to degrade the tunnel oxide) and a negative voltage gate stress (to reveal the SILC). An empirical SILC parameter has been defined as the lowest cell V/sub t/ in the parallel NVM array. This method has been implemented as part of end-of-line measurements in Philips embedded flash processes, and has been proven to be very effective and powerful in experimental split analysis, process reliability monitoring/control, and process transfers.

A qualification strategy for advanced embedded non-volatile memory technology has been revealed. This strategy consists of: a thorough understanding of the requirements, extensive use and frequent update of the FMEA (failure mode effect analysis), a qualification plan with excellent coverage of all the risk areas, implementing effective in-line and off-line measures and control, and check-off of all the tests with good results. With such a strategy in place, the Philips 0.18 /spl mu/m embedded flash technology has been successfully qualified for volume production.

In an advanced multi-process CMOS foundry it is strategically important to make use of an optimum reliability monitoring strategy, in order to be able to run well controlled processes. Philips Semiconductors Business Unit Foundries wafer fab MOS4YOU has developed an end-of-line ultra-fast reliability monitoring strategy, which provides a very fast and continuous feedback to the production line. In this work the advantages of such strategy are discussed by means of example cases, including hot-carrier reliability and a new end-of-line monitoring tool for non-volatile memory reliability.

The few fast bits, resulting from stress induced leakage current, that are found in a memory array limit lifetime of an entire device. Instead of classical temperature accelerated tests, 'simple' gate stress represents therefore the correct method to study the advanced non-volatile memory retention behavior. In this paper a model is proposed to predict the memory lifetime under use conditions based on accelerated gate stress measurements. The model considers a statistical approach, in order to overcome the erratic behavior of fast bits. It enables predicting the lifetime of memory products as function of memory size and number of write/erase cycles. Application of the model is discussed as well as a wafer level implementation form.

The five papers in this special issue were selected from the IEEE International Integrated Reliability Workshop (IIRW) 2008, held on October 12-16, 2008, near South Lake Tahoe, CA.

The 14 invited papers in this special issue were selected from the International Integrated Reliability Workshop (IIRW), which was held on October 16-19, 2006 at the Stanford Sierra Camp on the shores of Fallen Leaf Lake near South Lake Tahoe, CA.

It is well known that the light absorption in an amorphous silicon solar cell can be enhanced by applying textured transparent conductive oxide (TCO) substrates. However, the degree of the enhancement depends on the optical and surface properties of the TCO substrates: the refractive index n((lambda) ), the extinction coefficient k((lambda) ), the thickness d of the layer and the root mean square (rms) roughness (sigma) r of the rough surface. Because light scattering takes place at the rough surface, the transmittance spectroscopy cannot be directly applied to determine the TCO layer properties. We have studied the light scattering at the rough TCO surfaces. Based on our analysis, the reflected and transmitted light at a rough interface consists of a specular part and a diffused part. The specular reflectance and transmittance depend on the optical and surface properties of the TCO layer. We have developed a procedure to extract the optical and surface properties from the measured specular reflectance and transmittance. This extracting procedure and the results are presented in this paper.© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

In the course of developing amorphous silicon based solar cells, it is very important to know the profile of photo-generation rate in the device. This profile is strongly dependent on the optical properties of all the layers, the interface properties, and the incident light spectrum. In the case of a solar cell with flat interfaces, the interference effect at long wavelengths should be taken into account. The light absorption can be optimized at a certain layer thickness. However, in the case of a solar cell with a textured substrate, the problem becomes more complicated since light will be scattered at several rough interfaces. We have studied the light scattering at the rough interfaces in typical amorphous silicon solar cells, developed a computer model to simulate the optical behavior of a multi-layer system with rough interface and simulated amorphous silicon based solar cells with different structures: glass/TCO/pin(a- Si:H)/Ag, glass/TCO/pin(a-Si:H)/pin(a-Si:H)/Ag, glass/TCO/pin(a-Si:H)/TCO/Ag, and ITO/pin(a-Si:H)/TCO/Ag. In this paper, we present the method and the results of our optical modeling of amorphous silicon based solar cells. This modeling is performed for cells with flat or textured substrates.© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

The increasing complexity of hydrogenated amorphous silicon (a-Si:H) based solar cells requires continuous extending and testing of the computer models which are used for their simulation. The calculation of the defect states density in the bandgap of a-Si:H based on the defect pool model (DPM) has been rally implemented in the ASA (Amorphous Semiconductor Analysis) computer program developed at Delft University of Technology. We used the technique of inverse modelling to verify the DPM and to calibrate it by fitting the dark and illuminated J-V characteristics of a single-junction a-Si:H solar cell fabricated at Utrecht University. The DPM was also used in simulating the absorption coefficient of a-Si:H layers. Using the DPM for the defect states distribution, a good agreement between simulated and measured data was obtained. The values of the material parameters needed for obtaining the best fits are more realistic than using a conventional model for the defect states distribution.