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This paper describes the design of a 155m long-span hangar for Xiamen Taikoo Aircraft Maintenance Base. The roof structure adopted is a steel space truss and front arch frame with prestressed concrete tie. Although the suspended loading is over 1,000 tons, the heaviest among the hangars in China, the steel consumption is quite low due to the adopted rational layout and structural type. The paper introduces the measures taken in the design of the arch frame, H-section bolted plate joints, welded hollow spherical joints, prestressed tie and supports. Finally, wind tunnel test results for the hangar are briefly introduced.

Batcher's odd-even merging network can be easily implemented on hardware. And its parallel working between the comparator is very beneficial to play the advantages of hardware such as high efficiency and high speed. These make it as the most widely used sort algorithm. In this paper, FPGA is used to implement Batcher's odd-even merging network, solving the problems of traditional design. And the scalability of Batcher's odd-even merging network is also studied in this paper. The end results show that Batcher's odd-even merging network can be used to not only sort and classify the data, but also fast complete the parallel data packets distribute.

This article mainly describes a way of designing a parallel and highly pipelined Cyclic Redundancy Code (CRC) generator. The design can handle five different channels at an input rate of 2Gbps each. The generated CRCS are compatible with the 32-bit Ethernet standards. This circuit has been implemented with the chip EP2C35F672C6 of ALTERA using the properties of Galois Field. The synthesis results show that the design can meet the needs of high-speed data integrity check.

Along with the rapid application of large-scale integrated circuit and computer system is growing by geometric series, the boundary between hardware and software has blurred. EDA, a novel technology arisen in recent years has been challenged with the traditional hardware design, because the original method and mode cannot satisfy modern hardware system design. In this paper, we implement the complex design in a new way, where the programmable logic undoubtedly becomes the best suited technology.

This paper uses the similarity between SHA-224 and SHA-256 algorithms to design the SHA-224/256 IP core oriented Digital Signature. The IP core uses parallel structure and pipeline technology to simplify the hardware design and improve the speed by 26%. Finally this IP core is implemented on the Altera’s FPGA EP2C20F484C6 chip. And its simulation result can run rightly under the 100MHz frequency. This IP core can be widely used in the data integrity and consistency verification, pseudo random number generation and other areas of cryptography.

This article is based on the new standard, uses the FPGA device opening, adopts FPGA technique of EDA to build 64 bits decimal floating multiplier model. And in this article, we mainly use DPD codec and BCD new codec and Signed-Digit radix-5 to process coefficient. At last, we use Decimal 32:2 CSA algorithm to process partial product. This effectively increases the computing speed and accuracy. As the new standard revision and widespread application of the decimal floating-point multiplication operations, this design has a certain practical significance in the medical and financial sectors, as well as image processing technology.

This paper introduces the principle of AES algorithm and the detailed description and implementation on FPGA. This system aims at reduced hardware structure. Compared with the pipeline structure, it has less hardware resources and high cost-effective. And this system has high security and reliability. This AES system can be widely used in the terminal equipments.

This article mainly describes a way of designing an efficient pseudo-random number generator. Combining that the cellular automaton has many characteristics, such as simple rules of the component units, the local connectivity of units, the high degree of parallelism in information processing, and the complicated global characteristics, we use the rule 30 of one-dimensional cellular automaton to drive the state change. Finally, the pseudo-random numbers produced from the generator are tested the performance. And the results show that this design can be better applied to cryptography to ensure information technology and network security[1].