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We present a comprehensive study of bias temperature instability (BTI) in GaN MOSFETs under moderate positive and negative gate bias stress. We investigate the evolution of threshold voltage (V T ), maximum transconductance (g m,max ), and subthreshold swing (S). Our results show a universal continuous, symmetrical, and reversible VT shift and gm,max change as gate stress voltage (VGS,stress) increases from -5 to 5V at room temperature. The time evolution of V T is well described by a power law model. The voltage dependence, time dependence, and temperature dependence of our results suggest that for moderate gate bias stress, positive BTI and negative BTI are due to a single reversible mechanism. This is electron trapping/detrapping in preexisting oxide traps that form a defect band very close to the GaN/oxide interface and extend in energy beyond the conduction band edge of GaN and below the Fermi level at the channel surface at 0 V.

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016., Cataloged from PDF version of thesis., Includes bibliographical references (pages 109-116)., GaN is a promising alternative to Si for transistors for power electronics. For high-voltage applications, the GaN high electron mobility transistor with insulated gate (MIS-HEMT) is an attractive transistor structure because of its high breakdown voltage combined with low gate leakage current. Impressive device performance has recently been reported. However, before GaN MIS-HEMTs cab be deployed in the field, reliability and stability issues need to be solved. In particular, the threshold voltage (VT) instability under high voltage and temperature stress, sometimes referred to as bias-temperature instability (BTI), is a serious concern. The physical mechanisms responsible for BTI in GaN MIS-HEMT are not well understood. This is mainly because of the complex gate stack with multiple layers and interfaces, which presents many trapping sites with complex dynamics. In this work, a simpler GaN MOSFET structure is used to isolate the role of the gate oxide and the oxide/GaN interface in BTI. Using a carefully designed benign characterization approach, we have studied in detail the response to positive and negative gate bias stress of GaN MOSFETs with various gate dielectrics. This has allowed us to postulate relevant physical mechanisms. For positive gate stress (PBTI), positive VT shifts are caused by a combination of electron trapping in pre-existing oxide traps and trap generation either at the oxide/GaN interface (SiO₂/GaN) or in the oxide close to the interface (A1₂O₃/GaN). For negative gate stress (NBTI), three degradation mechanisms are proposed. In low-stress regime, recoverable electron detrapping from pre-existing oxide traps takes place resulting a temporary negative VT shift. In mid-stress regime, a transient positive VT shift is probably caused by electron trapping in the GaN channel under the edges of the gate. In high-stress regime, there is a permanent negative VT shift, which is consistent with interface state generation. In addition, we have confirmed t, by Alex Guo., Ph. D.

We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO[subscript 2] or a composite SiO[subscript 2]/Al[subscript 2]O[subscript 3] bilayer were studied. Our research has targeted the evolution of threshold voltage (V[subscript T]), subthreshold swing (S) and transconductance (g[subscript m]) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive V[subscript T] shift (ΔV[subscript T]) in both gate dielectrics under positive gate stress. In devices with a SiO[subscript 2] gate oxide, we have found that ΔV[subscript T] is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO[subscript 2]/Al[subscript 2]O[subscript 3] gate oxide, on the other hand, ΔV[subscript T] is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012., Cataloged from PDF version of thesis., Includes bibliographical references (p. 65-66)., As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V compound semiconductor channel are of great interest. Specifically, designs with an InGaAs channel have shown promising results for N type MOSFETs. In a new generation of III-V MOSFETs, one of the key challenges is to shrink device footprint while improving transistor's electrical performance. For future technology nodes, the gate length of MOSFETs needs to shrink below 10 nm, and the source and drain contacts must also decrease to a comparable dimension. A concern about contact scaling is the increase of source resistance. It is predicted that the source resistance will increase exponentially when the contact length is decreased to the nanometer scale regime. In order to understand the issues associated with source contact scaling to the nanometer regime, we have developed a fabrication process for nanometer scale TLM test structures to InGaAs/InAlAs heterostructures for MOSFETs. To analyze these structures, we have also developed a 2D circuit network. After measuring the fabricated devices, the model has been used to extract the relevant electrical parameters that characterize these structures. We have obtained a specific contact resistivity of (0. 116 +/- 0.058) [omega] - um². For Mo/n+-InGaAs contacts, to the best of our knowledge, this is the lowest value reported to date. The fabrication process and the theoretical model presented in this study should help future III-V CMOS scaling research and development., by Alex Guo., S.M.