Positive-bias temperature instability (PBTI) of GaN MOSFETs

We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO[subscript 2] or a composite SiO[subscript 2]/Al[subscript 2]O[subscript 3] bilayer were studied. Our research has targeted the evolution of threshold voltage (V[subscript T]), subthreshold swing (S) and transconductance (g[subscript m]) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive V[subscript T] shift (ΔV[subscript T]) in both gate dielectrics under positive gate stress. In devices with a SiO[subscript 2] gate oxide, we have found that ΔV[subscript T] is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO[subscript 2]/Al[subscript 2]O[subscript 3] gate oxide, on the other hand, ΔV[subscript T] is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.