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This is an overview of the data products and other resources available through NASA's LAMBDA site https://lambda.gsfc.nasa.gov/. An up-to-date version of this document, along with code tools actively maintained and developed by LAMBDA staff, can be found on the LAMBDA GitHub page at https://github.com/nasa-lambda/lambda_overview. New data products and other updates are announced on LAMBDA's twitter account at https://twitter.com/NASA_LAMBDA. If you have questions or suggestions relating to LAMBDA, or are interested in joining a LAMBDA advisory group, please contact us using the form here: https://lambda.gsfc.nasa.gov/contact/contact.cfm., Comment: 3 pages, 2 figures; this is an overview prepared by the LAMBDA team to provide information about the public resources available to the community through the LAMBDA site, not a journal submission. Revised September 2024 to correct broken or outdated links and update author list (LAMBDA team members), plus other minor improvements

This paper discusses the technical aspects of and the project background for the NASA Image exchange (NIX). NIX, which provides a single entry point to search selected image databases at the NASA Centers, is a meta-search engine (i.e., a search engine that communicates with other search engines). It uses these distributed digital image databases to access photographs, animations, and their associated descriptive information (meta-data). NIX is available for use at the following URL: http://nix.nasa.gov./NIX, which was sponsored by NASAs Scientific and Technical Information (STI) Program, currently serves images from seven NASA Centers. Plans are under way to link image databases from three additional NASA Centers. images and their associated meta-data, which are accessible by NIX, reside at the originating Centers, and NIX utilizes a virtual central site that communicates with each of these sites. Incorporated into the virtual central site are several protocols to support searches from a diverse collection of database engines. The searches are performed in parallel to ensure optimization of response times. To augment the search capability, browse functionality with pre-defined categories has been built into NIX, thereby ensuring dissemination of 'best-of-breed' imagery. As a final recourse, NIX offers access to a help desk via an on-line form to help locate images and information either within the scope of NIX or from available external sources.

Current design tools for digital circuits and systems are not well-integrated among the behavioral, gate, and transistor levels of design. Ulysses is a prototype software system that consists of a description language, a description compiler, and a simulator that make no distinction among these levels. The language is uniform over the entire range of logical descriptions, the description is hierarchical with no fundamental restrictions on depth or mixing of levels, and the simulator is fully integrated with the description. The structure of the language, compiler, and simulator are described in terms of their relationships to the abstractions of physical systems that are made in order to create logical descriptions and models of behavior.

The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk process. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.

Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.

The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk processes. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used in this study contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.

Random-fault densities measured in array of standard structures. Test pattern is array of standard circuit elements built into circuit chip along with, or in lieu of, integrated circuit objective process. Measurements on ray made and interpreted so fabrication process can be corrected as necessary.

Microelectronic test chips contain a number of test structures that are used for a variety of purposes in fabricating integrated circuits. For convenience, their use is divided into six groups: layout-rule evaluating, process-parameter extraction, device-parameter extraction, circuit-parameter extraction, initial-fabrication failure analysis, and reliability failure analysis. A given test structure can be used to gather information in a number of these groups. Examples are given here of the kinds of parameters that can be obtained in each of these groups. A table is included summarizing various device failures common to bulk CMOS and indicating failure mechanisms appearing after wafer fabrication and after stress.

It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

Integrated-circuit devices using the Ti/W/Au metal system are subject to failure mechanisms based on electrolytic corrosion. The migratory gold resistive short (MGRS) failure mode is one example of this mechanism and results in the formation of filamentary or dendritic deposits of gold between adjacent stripes on the IC chip. This reaction requires the presence of a sufficient amount of water, a bias voltage between adjacent stripes, and the activation of the cathodic (-) stripe. Gold ions are transported from anode to cathode through a film of moisture adsorbed on the surface of the chip; halide ions are probably involved in the transfer. Their presence is verified experimentally by X-ray photoelectron spectroscopy. Some of the chemical and electrostatic factors involved in the MGRS mechanism are discussed in this paper, including the questions of a threshold level of moisture and contamination.

Ni-Cr content and variability in Ivory Coast tektites using atomic absorption and X ray emission techniques