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This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (001) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger-Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature., QC 20100525

Mobility and low-frequency (LF) noise were studied in tensile strained Si n- and pMOSFETs fabricated on relaxed SiGe virtual substrates. Both the impact of the channel orientation ((110) or (100) on (100) Si) and the tensile strain were carefully investigated. Two types of virtual substrates were used; a thin relaxed SiGe layer (20% Ge) and a thick one (27% Ge). The strained Si nMOSFETs fabricated on the thin substrate showed similar LF noise level as in the reference devices, whereas the thick substrate caused severely increased LF noise in the nMOSFETs. The latter was linked to the higher Ge concentration and explained by possible misfit dislocations and increased defect densities, likely resulting from strain relaxation caused by ion implantation damage. On the other hand, considerably lower LF noise was achieved in the pMOSFETs on the thick SiGe. The channel orientation was not found to have a significant influence on the LF noise performance in any of the studied devices., QC 20100525

Epitaxial layers of Silicon Germanium Carbides, SiGe(C), have entered mainstream Silicon processing, forming base regions in heterojunction bipolar transistors. There also are exciting prospects for SiGe(C) having an impact on MOS technologies. In both cases heteroepitaxial layers enable very significant performance enhancements at the device and circuit level. A related area and a familiar hot issue is silicon epitaxy for device active regions in MOS technologies where tightly controlled doping distributions can be incorporated to facilitate device function at deep submicron channel lengths. CVD is a preferred epitaxy deposition technique for production; currently LP-CVD and UHV-CVD dominate. Each of these techniques demand much of the technology and have their respective strengths and weaknesses. Issues regarding matrix and doping control, uniformity, blanket and selective area growth, and throughput (a sensitive area) will be addressed. Also in the CVD portfolio is LEPE-CVD, a recent contender for the production arena that has the ability to access very high deposition rates. Such rates are required in depositing relaxed buffer layer material required as virtual substrates' for higher Ge content layers. SS-MBE, traditionally the favorite technique for research, also has distinct possibilities for development as a production tool. Here the issues relate primarily to throughput and system design, and (surprisingly) matrix profile control. These techniques will be outlined and reviewed in this paper along with issues that determine their development as the competition heats up in epitaxy, and as more complex and high Ge content structures are needed to progress Si technology to new performance heights and application areas. (11 figures, 6 refs.), Paper presented at the Workshop on MBE and VPE Growth, Physics, Technology (4th), held in Warsaw, Poland, on 24-28 Sept 2001. Pub. in THIN SOLID FILMS: An International Journal on the Science and Technology of Condensed Matter Films, v412 n1-2 p44-49, June 3, 2002. This article is from ADA412911 THIN SOLID FILMS: An International Journal on the Science and Technology of Condensed Matter Films. Volume 412 Nos. 1-2, June 3, 2002. Proceedings of the Workshop on MBE and VPE Growth, Physics, Technology (4th), Held in Warsaw, Poland, on 24-28 September 2001