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High Numerical Aperture (NA) EUV lithography will require very thin resist films. This reduction in thickness will challenge most metrology techniques, except for Atomic Force Microscopy (AFM). Indeed, thinner resist films allow AFM to reach a better depth accuracy and a higher throughput. In this work, we demonstrate the capabilities of AFM metrology on 16-nm half-pitch resist lines obtained with 5 resist film thicknesses ranging from 10 to 30 nm. As we show, AFM provides relevant information about the pattern dimensions (resist height, line top roughness) as a function of exposure dose, and even about the bottom trench roughness on films with thickness < 10 nm.

Background: Decomposing an observed variation in critical dimension (CD) into its sources of variation is an important analysis, but it is often tedious and prone to error. For EUV processes, identifying the magnitude of stochastic variations is especially important and relevant. Aim: An automated process for decomposing CD errors into its sources will aid in the analysis of a specific EUV process. Approach: MetroLER offline metrology software has been updated to perform automated sources of variation analysis, including the measurement and subtraction of systematic and random components, such as across-SEM-field signatures and random metrology errors. Results: For a staggered array of 24 nm contacts holes on an 80X46 nm pitch, the total CD uniformity (CDU) of about 3.3 nm included a global CDU across wafer of about 1.0 nm, a systematic mask contribution of 1.7 nm, systematic metrology contribution of 1.0 nm, and a random metrology contribution of 0.67 nm (all 3σ), leaving a stochastics-only CDU of about 2.6 nm. Conclusions: Careful consideration of the systematic and random components in CD measurement variations enables measurement of the stochastic contribution to a state-of-the-art EUV contact printing process. The contribution of metrology error

Wafer fab mask inspection is facing new challenges in the era of Extreme Ultraviolet Lithography (EUVL). Mask qualification methods in use for ArF lithography are reticle verification based on wafer prints or defect inspection on Deep Ultraviolet (DUV) mask inspection tools. The latter is the industry preference in most cases. To implement this established methodology for EUV masks with pellicle, the pellicle must have transmission that enables inspection for defect detection. In this work we test the viability of a DUV mask inspection platform to image and inspect an EUV mask with a Carbon Nanotube (CNT) based pellicle [1]. Pellicles are used to keep particles off the patterned side of the photomask. For DUV and longer exposure wavelengths, polymers with transmission above 99% are routine. For EUV wavelengths, identifying a transparent, mechanically robust film that is compatible with EUV exposure environments has been challenging. Commercially-available EUV pellicles for lithography are p-Si based[2]. This pellicle type achieves the critical protection of the mask but induces a significant productivity loss due to EUV light absorption. The critical need for a highly-transmissive pellicle will increase with advanced nodes that put more pressure on uniformity specifications and throughput. In this arena, CNT based pellicles exceed the required transmission for High-Volume Manufacturing (HVM) and show promise towards production adoption [3]. DUV light absorption is relevant for mask inspection. DUV light is absorbed by the p-Si pellicle, while the CNT has high transmission in this wavelength region as well, making mask inspection of EUV masks with pellicles possible on existing DUV inspection tools, such as Applied Materials Aera5TM. In order to understand the impact of CNT pellicle on DUV inspection, a controlled study was performed by Applied Materials in cooperation with imec. The study consisted of various system measurements and extensive application qualification. Aera5TM inspection results on a Programmed Defect Mask (PDM) with a full field CNT pellicle will be presented. The results with pellicle are comparable to the reference no-pellicle inspection and meet the same detection sensitivity. Detection optimization Best-Known Methods (BKM) developed on EUV masks without pellicles proved to be effective. These include, but are not limited to, aperture shaping, defocus and polarization. Moreover, the imaging and main system components performance were examined, and no impact was observed.

Background: Random and systematic errors found in CD-SEM tools affect the measurement of roughness in dramatically different ways than the measurement of the average critical dimension. Aim: In order to increase the accuracy of roughness measurements, monitor the health of CD-SEM tools, and improve CD-SEM tool matching, it is important to measure and remove the impact of random and systematic errors from the measurements. Approach: Several different CD-SEM tool systematic errors have been identified, but the scan error signature in particular was found to be very relevant. This signature is measured using the mean contour of many properly sampled features and can be used as the target edge for roughness calculations in order to remove this error. Results: Using six different CD-SEM tools and a large data set of across-wafer, across-scanner-field measurements of the same wafer, each CD-SEM tool was found to have a unique CD-SEM signature. Subtracting off this error signature significantly improved the accuracy of the roughness measurements and the CD-SEM tool-to-tool matching. It also identified one tool as being problematic, requiring further attention. Conclusions: Measurement and characterization of the CD-SEM scan error is a powerful tool, along with measurement and removal of random edge detection noise, for monitoring CD-SEM tool health, matching different CD-SEM tools, and improving the accuracy of line-edge and linewidth roughness measurements.

As the development of Extreme Ultraviolet Lithography (EUVL) is progressing toward the sub-10nm generation, the process window becomes very tight. In this situation, local Critical Dimension (CD) variability including stochastic defect directly affects the yield loss, and it is very important to inspect/measure all patterning area of interest on chip for the process verification. In this paper, by combining Area Inspection SEM (AI-SEM) with large Field Of View (FOV) and Die-to-Database-base (D2DB) technologies, we show a comprehensive solution for fast inspection and precise massive CD measurement of EUV characterized features, such as After Development Inspection (ADI) hole pattern, and aperiodic 2D Logic pattern. Also, a big data analysis consisting of multiple CD indices output by AI-SEM, a new process window by multivariable analysis is discussed. Furthermore, Machine Learning (ML) -based inspection and metrology to maximize imaging speed, is also reported.

Over the years, the reduction in the size of semiconductor devices has made their performances extremely sensitive to small differences between printed structures and intended design. As a consequence, metrology equipment manufacturers are nowadays proposing new tool configurations, able to ensure quality control in such a challenging environment by generating massive multi-properties measurement sets from inspected wafers. However, the unprecedented amount of acquired measurements and their intrinsic diversity creates a new challenge in terms of data analysis. In this work, we propose an analysis method suitable for massive multi-descriptors data sets and apply it to the processing of measurements acquired on the GS1000, the latest generation e-beam metrology tool from Hitachi. This new approach is based on the Parallel Coordinates Plot (PCP). The PCP representation is very efficient to condensate multidimensional data into a single plot, but not adapted to large data sets due to over-plotting problems. To overcome these issues, we have developed specific strategies to enable PCP to be efficient on massive data analysis by both extracting neighbors' properties by median depiction and the multi-properties dispersion. The experimental validation has been carried out over 1.7 billion Contact Hole (CH) measurements acquired on a test wafer. 28 different properties have been quantified from the e-beam images for each pattern and grouped into 3 categories: size area, edge placement error, and gap. The analysis of the full data set with the proposed methodology clearly showed the FEM fingerprint and allowed us to determine the process window based on the multi-criteria analysis. By combining the PCP with an Artificial Neural Network (ANN) we were able to model accurately the stochastic cliffs defects' density.

CD-SEM images inherently contain a significant level of noise. This is because a limited number of frames are used for averaging, which is critical to ensure throughput and minimize resist shrinkage. This noise level of SEM images may lead to false defect detections and erroneous metrology. Therefore, reducing noise in SEM images is of utmost importance. Both conventional noise filtering techniques and recent most discriminative deep-learning based denoising algorithms are restricted with certain limitations. The first enables the risk of loss of information content and the later mostly requires clean ground-truth or synthetic images to train with. In this paper, we have proposed an U-Net architecture based unsupervised machine learning approach for denoising CD-SEM images without the requirement of any such ground-truth or synthetic images in true sense. Also, we have analysed and validated our result using MetroLER, v2.2.5.0. library. We have compared the power spectral density (PSD) of both the original noisy and denoised images. The high frequency component related to noise is clearly affected, as expected, while the low frequency component, related to the actual morphology of the feature, is unaltered. This indicate that the information content of the denoised images was not degraded by the proposed denoising approach in comparison to other existing approaches.

In the extreme ultraviolet (EUV) lithography process, stochastic defects are randomly generated and can have a significant impact on the yield of high-volume manufacturing (HVM) when printed even at an extremely low probability down to parts per trillion (ppt) level. In this field, electron beam inspection (EBI) tools are regarded as a promising option to detect killer defects with enough capture rate. However, EBI requires a longer inspection time and it is pointed out as the current limitation of EBI. To overcome this limitation, throughput optimization and data collection strategy must be prepared to push the bounds of EBI capability. In this paper, we study the probability of EUV stochastic defect and its statistical signature in massive data using EBI. Tool performance for detecting defects is maximized by investigating the impact of different parameters of scanning electron microscopy (SEM) on throughput and defect capture rate. After performance verification, we demonstrate massive metrology and inspection performance of Die to Database Edge Placement Error (D2DB EPE) to extend the prediction range of stochastic defect probability down to the order of 1 defect/mm2. The method is applied to EBI results on EUV processed pitch 32nm line and space (L/S) pattern to prove the necessity of massive e-beam data analysis of low-level defectivity and intra-field variation.

Things are drastically changing in the field of metrology. The main reason for that is related to the daunting specification requirements for metrology imposed by high Numerical Aperture Extreme Ultraviolet Lithography (high NA EUVL). We observe a variety of new generation e-beam tools proliferating in imec unique ecosystem, from in-line Transmission Electron Microscope (TEM) to Voltage Contrast (VC) overlay tools, from Die To Database (D2DB) large area Scanning Electron Microscope (SEM) to high-voltage SEM, from Artificial Intelligence (AI)-based inspection tools to massive data acquisition e-beam system. We are facing a renaissance of e-beam metrology. In this paper, we are going to describe the challenges as well as the latest evolutionary developments of e-beam metrology in the semiconductor industry.

A method to perform Optical Proximity Correction (OPC) model calibration that is also sensitive to lithography failure modes and takes advantage of the large field of view (LFoV) e-beam inspection, is presented. To improve the coverage of the OPC model and the accuracy of the after development inspection (ADI) pattern hotspots prediction - such as trench pinching or bridging in complex 2D routing patterns - a new sampling plan with additional hotpot locations and the corresponding contours input data is introduced. The preliminary inspected hotspots can be added to the traditional OPC modeling flow in order to provide extra information for a hotspot aware OPC model. A compact optical/resist 3D modeling toolkit is applied to interpret the impact of photoresist (PR) profiles, as well as accurate predictions of hotspot patterns occurring at the top or bottom of the PR. A contour-based modeling flow is also introduced that uses a site or edge based calibration engine, to better describe hotspot locations in the hotspot aware OPC model calibration. To quantify the improvement in pattern coverage in the modeling flow, feature vectors (FVs) analysis and comparisons between the conventional and the hotspot aware OPC models is also presented.[1] The time and cost of using conventional Critical Dimension Scanning Electron Microscope (CD-SEM) metrology to measure such a large amount of CD gauges are prohibitive. By contrast, using LFoV e-beam inspection with improved training algorithm to extract fine contours from wafer hotspots, a hotspot aware OPC model can predict ADI hotspots with a higher capture rate as compared to main feature OPC model. Presumably, a hotspot-aware modeling flow based on LFoV images/contours not only benefits users by improving the capture rate of the lithography defects, but also brings the advantages to the failure mode analysis for the post-etch stage.

Local critical dimension uniformity (LCDU) for contact holes may be correlated with stochastic defects (missing or merged holes), but metrology noise will bias the LCDU measured by a CD-SEM. In this work, large contact hole data sets will be collected with varying SEM measurement recipes, such as different numbers of frames of averaging. Additionally, multiple measurements of the same after-etch features will be used to quantify the impact of metrology noise on the biasing of measured LCDU. Finally, a recommendation will be made as to an approach that minimizes, or eliminates, bias in LCDU measurements.

For the introduction of directed self-assembly (DSA) process into high volume manufacturing, the roughness of pattern is one of main check points. The focus of this study is to understand the origin of DSA roughness and to discuss the strategies to improve DSA-specific roughness. 3X DSA LiNe flow with PS-b-PMMA was used as a model case. Unbiased line edge roughness (LER) and linewidth roughness (LWR) were measured using power spectral density (PSD) analysis on CDSEM images. We found that low frequency LER is particularly sensitive to the assembly conditions. By optimizing material and process conditions, unbiased LWR was reduced by about 10%, while unbiased LER was reduced by about 15%.

Electron beam (EB) metrology of Ge channel gate-all-around (GAA) FET (field effect transistor) was investigated. Ge-GAA FET is one of the promising candidates for high performance pMOS device of future node. Ge is superior to Si in hole mobility which can be enhanced further by applying compressive channel strain in GAA structure with SiGe strain relaxed buffer (SRB). Coincide with this advantage, channel buckling could happen more easily. Thus, a monitoring method of channel buckling is required. Chemical instability of Ge is another issue in fabrication process. It is suspected that EB irradiation during SEM inspection could cause the deterioration of device performance. On this background, following two evaluations were performed. The first one is quantitative evaluation of channel buckling. It is found that the channel buckling can be quantified with a proposed buckling index. The second one is assessment of the EB-induced damage on the electrical properties. The results showed that EB irradiation on Ge channels does not affect the device performance when the device is annealed adequately. In conclusion, EB metrology is effective for the evaluation of channel buckling and applicable to Ge channels without deterioration of the device performance.

In this work we show measurement results on EUV vias through full process integration; after litho (ADI), after etch (AEI) and after CMP polish (API) for a wide range of designs (regular arrays, logic, SRAM, and alignment and overlay mark designs) on a single damascene via scheme. Physical inspection (top view) and voltage contrast (VC) measurements are used to determine number of via failures at different stages of the process flow. While the physical inspection reveals vias missing and merging on top layer (at resist level ADI or hard mask AEI) the VC also can show failing vias AEI at the bottom of the via or in general failing vias API due to failing via fill during metallization and etch. Different metallization schemes including TaN vs TaNRu liners and Co vs Cu plating and CMP were compared using VC. Quantification of VC anomalies in the inspection images allows judgement of the metal fill on the single damascene via patterning across the different structures. The number of missing and merging vias AEI and API is used as a proxy for yield and this metric was used to drive process optimization. Given the large FoV of images collected on eP5 tool with a field of view 8µm x 8µm - 12µm x 12µm with 1nm or 2nm pixel size it is possible to determine both CD and defects in the same inspection for a substantial number of vias in a relatively short inspection time. Furthermore the VC inspection method is applied to an imec vehicle consisting of via chains at 32nm pitch to determine and localize failures along the via chain.

As the lithographically manufactured nanostructures are shrinking in size, conventional techniques, such as Scanning Electron Microscopes and Atomic Force Microscopes reach their resolution limits [1]. Novel inline scatterometry techniques not only provide the opportunity to bridge this gap, but they can also advance characterization of the lithographic process. The particular, Critical-Dimension Grazing incidence Small Angle X-ray Scattering (CDGISAXS) has emerged as one such promising modality to extract the profile of line gratings [2]. With the advent of brighter x-ray sources with tunable energies and faster detectors, there is a possibility for combining fast X-ray acquisition with high-speed data treatment to reach the timescale for an effective in-line characterization method. Due to recent progress in the ability to model data acquired from CD-GISAXS, we extended our model in order to study the impact of roughness. A set of twelve samples were studied. First, periodic line edge roughness (LER) and line width roughness (LWR) were measured, leading to the apparition of several semi-circle of Bragg spots as illustarted on Figure 1a. Using HIpGISAXS software, the GISAXS patterns were reproduced, allowing the extract of the periodicity of the roughness. On the second part of the line gratings, aperiodic roughness were designed with different frequencies and amplitudes. These samples led to the superposition of a semi-circle of Bragg spots with a “palm tree” feature coming from the profile of the gratings, illustarted on figure 1b. In a fist step, we extracted the in-depth profile of the gratings by fitting the modulations of the palm tree, in a similar approach as the CD-GISAXS one. In a second step, we modeled the impact of the roughness on the CD-GISAXS pattern and proposed a model to extract the roughness amplitude and frequency. References: [1] ITRS (2013). International Technology Roadmap for Semiconductors, http://www.itrs.net/. [2] Freychet, G. et al. (2018) Proc. SPIE, 10585, 1058512. [3] Freychet et al. (2018) Nanoscale Horizons, submitted. [4] Chourou, S. T., Sarje, A., Li, X. S., Chan, E. R. & Hexemer, A. (2013). J. Appl. Cryst. 46, 1781–1795.

In the next generation SAOP (Self-aligned Octuplet patterning) process, the line width and LWR (Line Width Roughness) measurement of lines with sub-10 nm is required. We have already proposed a novel method of line width and LWR measurement with sub-nanometer uncertainty by using FIB (Focused Ion Beam) processing, and TEM (Transmission Electron Microscope) images as reference metrology. In the previous report, we applied the method to SAQP features. A specimen of the SAQP FinFET line and space device is coated with carbon and cut horizontally into a thin planar sample by the FIB sampling system. The thin sample is observed by using planar-TEM. The average PSD of LWR of SAQP FinFET sample at the upper and lower positions calculated from planar-TEM images. In this article, we apply the methodology to line width and roughness measurement of advanced features by SAOP process. The features are vertically or horizontally sliced as a thin specimen by FIB micro sampling system. LWR is calculated from the edges positions, and PSD (Power Spectrum Density) is analyzed for the reference metrology.

Background: The measurement of line-edge and linewidth roughness of small features for semiconductor manufacturing is commonly accomplished using a scanning electron microscope (SEM). But these measurements are biased by the noise inherent in SEM imaging. Aim: Unbiasing of roughness measurements is best accomplished by taking advantage of the frequency characteristics of the noise to measure and subtract it out. This requires the ability to detect edges in a noisy SEM image without the use of standard image filtering techniques . Approach: A physics-based inverse linescan model is used to robustly detect edges in high-noise SEM images without the use of filtering or image averaging. To validate the efficacy of SEM noise measurement and subtraction, rough features were measured under a wide variety of SEM settings, including number of frames of averaging and voltage. Results: In all cases, the vast majority of the measurement bias was properly subtracted out. Over a wide range of SEM settings the biased roughness varied by more than a factor of two, but the unbiased linewidth roughness varied by only a few percent. Conclusions: The approach of inverse-linescan edge detection followed by noise measurement and subtraction leads to reliable estimates of the true (unbiased) line-edge and linewidth roughness of features on the wafer. These unbiased estimates are quite insensitive to metrology tool settings over a reasonable range of values.

Extreme ultraviolet (EUV) materials are deemed as critical to enable and extend the EUV lithography technology. Currently both chemically amplified resist (CAR) and metal-oxide resist (MOR) platforms are candidates to print tight features on wafer, however patterning requirements, process tonality (positive or negative), illumination settings and reticle tonality (dark or bright) play a fundamental role on the material performance and in consequence on the material choice. In this work we focus on the patterning of staggered pillars using a single EUV exposure, and this by looking at the lithographic and etching performance of CAR and MOR platforms, using metrics as process window, local critical dimension uniformity (LCDU), pillar edge roughness (PER), pillar placement error (PPE) and (stochastic) nano-failures. As a bright field reticle shows a lower aerial image contrast to print pillars compared to the aerial image of contact holes using a dark field reticle, we also investigate alternative patterning solutions such as the tone reversal process (TRP) to pattern pillars from contact holes.

In order to meet the tight Line Width Roughness (LWR) requirements for advanced metrology nodes, it is critical to be able to identify what the fundamental sources of roughness are, so that they can be individually minimized. In fact, more and more efforts aiming to decouple mask and / or metrology contribution from wafer data have been recently reported [1]. However, these approaches often rely heavily on extensive mask characterization, something that is not always easily available. We propose here an alternative path to investigate and discriminate the root causes of LWR using only wafer data. It is based on Local Critical Dimension Uniformity (LCDU) decomposition [2], a methodology used to identify and quantify the individual LCDU contributors. The decomposition approach requires a smart sampling of the wafer print, in which an array of contact hole is measured in different dies multiple times. For such an approach to be successful, it is critical to ensure that the measurement locations are individually identified. Hence, it is necessary to anchor the metrology to a reference feature. A linear nested model [3] is then used to quantify the three main variability components (mask, shot noise, and metrology). This approach allows to sample thousands of features at mask, a task that would not be practically achievable through direct mask measurements. In this work, LWR decomposition is implemented for the first time. To this aim, 18nm lines at 36nm pitch, printed by EUV lithography, were used. We specifically worked with a pattern including programmed defects, used as anchoring features for the metrology. In order to limit the impact of the metrology noise, expected to be higher for lines as compared to CH, we sampled over 8000 anchored measurements per image (in the CH case, only 81 measurements per image were needed). The LWR decomposition results indicated the dominance of the metrology noise, as expected. In addition, the mask contribution was observed to be less relevant that the shot noise. To verify the accuracy of the LWR decomposition results, Power Spectral Density (PSD) analysis on wafer and mask SEM images was used. The metrology noise contribution was removed at both mask and wafer level using an un-biasing normalization of the PSD curves [4]. The comparison with the PSD analysis confirmed the feasibility of LWR decomposition, opening the way to a more effective diagnostic technique for roughness and stochastics.

Deep Learning (DL) techniques based on Denoising Convolutional Neural Networks (DeCNN) are applied in the denoising of SEM images of line patterns to contribute to noise-reduced (unbiased) LER nanometrology. The models of DeCNN are trained in a sufficiently large set of synthesized SEM images with controlled Gaussian and Poisson noise level. Due to the image-based nature of the DL approach, it can be combined sequentially with the state of the art PSD-based method especially for highly noisy images where the use of the PSD-based method alone fails. The results for test synthesized images show the high predicting capability of the DL assisted method for the commonly used LER parameters and functions (Rms, ξ, α, PSD) of the true (zero-noise) values revealing its potential for future use toward an unbiased LER metrology.

Electronic processes in extreme ultraviolet lithography are key to understand chemical reactions that lead to exposure of photoresist because of recent evidence that even very low kinetic energy electrons (Ek → 0 eV) might be very efficient in dissociating the molecules in photoresists. However, an assessment of the distribution of electrons involved in the cascade at kinetic energy approaching zero eV is not trivial in solid state. In this work, we use electron yield spectroscopy from thin photoresist films based on poly(hydroxystyrene) with and without photoacid generator (PAG). The results show that the addition of PAG boosts the electron yield by a factor 2 with respect to the polymer only photoresist. We then elaborate an analytical form of the transfer function that describes the physics of the photoemission by accounting for the energy distribution inside the photoresist material during exposure to extreme ultraviolet light. By fitting the model function to the spectroscopic data, we obtain an estimation for the distribution of electrons which lie inside the material at energy too low to be measured by an external detector, in other words the hidden tail of low energy electrons. For a quantitative comparison, we also use another approach based on MonteCarlo simulation of electronic scattering effects to calculate numerically the magnitude of the electron cascade. Using Chariot simulator, a statistically significant number of electronic trajectories (6 x107) was calculated and the energy distribution of electrons are compared both outside and inside the photoresist film.

© 2018 Society of Photo-Optical Instrumentation Engineers (SPIE). As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: line width roughness (LWR) specifications are expected to be 2 μm and the need to correct for scanning electron microscope (SEM) noise]. We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec roughness protocol - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such as LWR, everyone speaks the same language, which is not currently the case.

Power spectral density (PSD) analysis is playing more and more a critical role in the understanding of line-edge roughness (LER) and linewidth roughness (LWR) in a variety of applications across the industry. It is an essential step to get an unbiased LWR estimate, as well as an extremely useful tool for process and material characterization. However, PSD estimate can be affected by both random to systematic artifacts caused by image acquisition and measurement settings, which could irremediably alter its information content. In this paper, we report on the impact of various setting parameters (smoothing image processing filters, pixel size, and SEM noise levels) on the PSD estimate. We discuss also the use of PSD analysis tool in a variety of cases. Looking beyond the basic roughness estimate, we use PSD and autocorrelation analysis to characterize resist blur[1], as well as low and high frequency roughness contents and we apply this technique to guide the EUV material stack selection. Our results clearly indicate that, if properly used, PSD methodology is a very sensitive tool to investigate material and process variations

Accurate EPE (edge placement error) characterization is important for the process control of high-volume manufacturing at N5 BEOL and beyond. In a CD-SEM metrology, the accurate edge-to-edge measurements among multiple layers and/or SEM-Contour extraction are required for the accurate EPE characterization. One of the technical challenges in CD-SEM metrology is to control charging effects caused by EB-irradiation during SEM image acquisition. In this paper, the effects of new charge control methods (Special Scan and Faster Scan), which are implemented in the latest Hitachi CD-SEM (CG6300), were examined with EUV resist hole-patterns. It was confirmed that Special Scan showed a profound effect on the suppression of the charge-induced errors. We also demonstrated the effects of the Special Scan for CD measurements and Contour Extraction for the EPE characterization of block on SAQP (SAQP lines + EUV block) pattern at imec iN7platform. Consequently, Special Scan is expected to be the solution for the accurate EPE measurements by CD-SEM.

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

Use of ArFi lithography requires application-specific tuning to maximize patterning process windows. Previous investigations into the effects of light source bandwidth on imaging performance have provided the foundation for this work by identifying significant improvements in Exposure Latitude for reduced sensitivity to dose variations. This study will focus on the increase in image contrast that 200 fm light source E95 bandwidth enables on Self- Aligned Quadruple Patterning (SAQP) and Self-Aligned Double Patterning (SADP) core features. Focus of our investigation will be the understanding of roughness and profile variation through different exposure conditions.

The aim of this paper is to investigate the role of etch transfer in two challenges of LER metrology raised by recent evolutions in lithography: the effects of SEM noise and the cross-line and edge correlations. The first comes from the ongoing scaling down of linewidths, which dictates SEM imaging with less scanning frames to reduce specimen damage and hence with more noise. During the last decade, it has been shown that image noise can be an important budget of the measured LER while systematically affects and alter the PSD curve of LER at high frequencies. A recent method for unbiased LER measurement is based on the systematic Fourier or correlation analysis to decompose the effects of noise from true LER (Fourier-Correlation filtering method). The success of the method depends on the PSD and HHCF curve. Previous experimental and model works have revealed that etch transfer affects the PSD of LER reducing its high frequency values. In this work, we estimate the noise contribution to the biased LER through PSD flat floor at high frequencies and relate it with the differences between the PSDs of lithography and etched LER. Based on this comparison, we propose an improvement of the PSD/HHCF-based method for noise-free LER measurement to include the missed high frequency real LER. The second issue is related with the increased density of lithographic patterns and the special characteristics of DSA and MP lithography patterns exhibits. In a previous work, we presented an enlarged LER characterization methodology for such patterns, which includes updated versions of the old metrics along with new metrics defined and developed to capture cross-edge and cross-line correlations. The fundamental concept has been the Line Center Roughness (LCR), the edge c-factor and the line c-factor correlation function and length quantifying the line fluctuations and the extent of cross-edge and cross-line correlations. In this work, we focus on the role of etch steps on cross-edge and line correlation metrics in SAQP data. We find that the spacer etch steps reduce edge correlations while etch steps with pattern transfer increase these. Furthermore, the density doubling and quadrupling increase edge correlations as well as cross-line correlations.

Directed self-assembly (DSA) of block copolymer (BCP) thin films has been extensively researched as an alternative lithographic technology to enhance the resolution beyond the limitation of current lithography techniques.[1] One of the most critical factors need to be addressed for DSA process to be accepted at high volume manufacturing (HVM) is defect density of DSA pattern.[2] The defects of thermodynamically driven DSA process, such as the dislocation defects in LiNe flow, are known as kinetically trapped metastable structures.[3] Therefore, a key to eliminate those defects is to find out the effective kinetic pathway of assembly that enables BCP to reach to defect-free structure more easily. In addition to defect annihilation, easy pathway will also allow faster assembly, consequently reducing the cost of ownership of DSA process. The obvious approach for faster assembly in DSA process is to increase annealing temperature. In this study, we address the impact of annealing temperature on DSA process. First, increasing annealing temperature makes the free surface of a PS-b-PMMA film more PMMA preferential. Because of altered boundary condition at the top surface, more careful optimization of backfilling brush was required to maintain preferred orientation of BCP films. Second, the dimension of BCP is also affected by annealing temperature. Temperature dependency of BCP dimension was quantitatively investigated by CD-SEM and DSA-APPS Offline CD Measurement Software (Figure 1a). Based on the measured values, the dimension of chemical pattern is accordingly modified to achieve aligned DSA pattern (Figure 1b). We anticipate our finding from this study can be generally applied for other BCP systems. [1] Ruiz, Ricardo, Huiman Kang, Francois A. Detcheverry, Elizabeth Dobisz, Dan S. Kercher, Thomas R. Albrecht, Juan J. de Pablo, and Paul F. Nealey. "Density multiplication and improved lithography by directed block copolymer assembly." Science 321, no. 5891 (2008): 936-939. [2] Gronheid, Roel, Paulina Rincon Delgadillo, Hari Pathangi, Dieter Van den Heuvel, Doni Parnell, Boon Teik Chan, Yu-Tsung Lee et al. "Defect reduction and defect stability in IMEC's 14nm half-pitch chemo-epitaxy DSA flow." In SPIE Advanced Lithography, pp. 904905-904905. International Society for Optics and Photonics, 2014. [3] Hur, Su-Mi, Vikram Thapar, Abelardo Ramirez-Hernandez, Gurdaman Khaira, Tamar Segal-Peretz, Paulina A. Rincon-Delgadillo, Weihua Li, Marcus Muller, Paul F. Nealey, and Juan J. de Pablo. "Molecular pathways for defect annihilation in directed self-assembly." Proceedings of the National Academy of Sciences 112, no. 46 (2015): 14144-14149.

In the last year, the continuous efforts on the development of extreme ultraviolet (EUV) lithography has allowed to push the lithographic performance of the EUV photoresists on the ASML NXE:3300 full field exposure tool. Today imec N7 node (equivalent to foundry N5) is the first scaling node at which industry will likely insert EUV into production which will bring a reduction in processing steps therefore reducing total cost of ownership [1], increasing yield and reducing time to ramp. However, the high-volume-manufacturing (HVM) requirement to have a cost-effective low exposure dose photoresist ( To be effective during the lithographic EUV material screening phase for such tight pitches, it is necessary to implement complementary metrology analyses that can provide precise information on the resist roughness and a quick feedback on the quantification of nano-failures (nano-bridges, broken lines, merging or missing contacts) induced by a stochastic EUV patterning regime, the random nature of the light-matter interaction and consequent chemical reactions. Beside the traditional approach to characterize a resist with metrics as exposure latitude (EL%), depth of focus (DoF) and line-edge-roughness (LER) based on CDSEM measurements, we have used the power spectra density (PSD) [4] to get an unbiased value of the resist line roughness (LWR and LER) by using Fractilia metroLERTM commercial software. Further, we have used Stochalis imec software [5] to quantify patterning nano failures providing an early stage assessment on the patterning fidelity of the examined resists. We present the resist characterization results for 32nm dense line-space pattern on different substrates and for 36nm dense and orthogonal contact hole pitch pattern for different photoresists. Two positive tone chemically amplified (CA) resists have been identified at the exposure dose of 45mJ/cm2 and 33mJ/cm2 for logic (pitch 32nm dense line/space) and memory (pitch 36nm dense contact holes) use cases, respectively.

Metrology plays an important role in edge placement error (EPE) budgeting. Control for multi-patterning applications as new critical distances needs to be measured (edge to edge) and requirements become tighter and tighter in terms of accuracy and precision. In this paper we focus on imec iN7 BEOL platform and particularly on M2 patterning scheme using SAQP + block EUV for a 7.5 track logic design. Being able to characterize block to SAQP edge misplacement is important in a budgeting exercise (1) but is also extremely difficult due to challenging edge detection with CD-SEM (similar materials, thin layers, short distances, 3D features). In this study we develop an advanced solution to measure block to SAQP placement, we characterize it in terms of sensitivity, precision and accuracy through the comparison to reference metrology. In a second phase, the methodology is applied to budget local effects and the results are compared to the characterization of the SAQP and block independently.

In this paper, we propose to rethink the issue of LER characterization on the basis of the fundamental concept of symmetries. In LER one can apply two kinds of symmetries: a) the translation symmetry characterized by periodicity and b) the scaling symmetry quantified by the fractal dimension. Up to now, a lot of work has been done on the first symmetry since the Power Spectral Density (PSD), which has been extensively studied recently, is a decomposition of LER signal into periodic edges and quantification of the ‘power’ of each periodicity at the real LER. The aim of this paper is to focus on the second symmetry of scaling invariance. Similarly to PSD, we introduce the multifractal approach in LER analysis which generalizes the scaling analysis of standard (mono)fractal theory and decomposes LER into fractal edges characterized by specific fractal dimensions. The main benefit of multifractal analysis is that it enables the characterization of the multi-scaling contributions of different mechanisms involved in LER formation. In the first part of our work, we present concisely the multifractal theory of line edges and utilize the Box Counting method for its implementation and the extraction of the multifractal spectrum. Special emphasis is given on the explanation of the physical meaning of the obtained multifractal spectrum whose asymmetry quantifies the degree of multifractality. In addition, we propose the distinction between peak-based and valley-based multifractality according to whether the asymmetry of the multifractal spectrum is coming from the sharp line material peaks to space regions or from the cavities of line materis (edge valleys). In the second part, we study systematically the evolution of LER multifractal spectrum during the first successive steps of a multiple (quadruple) patterning lithography technique and find an interesting transition from a peak-based multifractal behavior in the first litho resist LER to a valley-based multifractality caused mainly by the effects of etch pattern transfer steps.

A methodology to evaluate the electrical contact between nanowire (NW) and source/drain (SD) in NW FETs was investigated with SEM voltage contrast (VC). The electrical defects were robustly detected by VC. The validity of the inspection result was verified by TEM physical observations. Moreover, estimation of the parasitic resistance and capacitance was achieved from the quantitative analysis of VC images which were acquired with different scan conditions of electron beam (EB). A model considering the dynamics of EB-induce charging was proposed to calculate the VC. The resistance and capacitance can be determined by comparing the model-based VC with experimentally obtained VC. Quantitative estimation of resistance and capacitance would be valuable not only for more accurate inspection, but also for identification of the defect point.

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

The miniaturization of semiconductors continues, importance of overlay measurement is increasing. We measured overlay with analysis SEM called Miracle Eye which can output ultrahigh acceleration voltage in 1998. Meanwhile, since 2006, we have been working on SEM based overlay measurement and developed overlay measurement function of the same layer using CD-SEM. Then, we evaluated overlay of the same layer pattern after etching. This time, in order to measure overlay after lithography, we evaluated the see-through overlay using high voltage SEM CV5000 released in October 2016. In collaboration between imec and Hitachi High-Technologies, we evaluated repeatability, TIS of SEM-OVL as well as correlation between SEM-OVL and Opt-OVL in the M1@ADI and V0@ADI process. Repeatability and TIS results are reasonable and SEM-OVL has good correlation with Opt-OVL. By overlay measurement using CV 5000, we got the following conclusions. (1)SEM_OVL results of both M1 and V0 at ADI show good correlation to OPT_OVL. (2)High voltage SEM can prove the measurement capability of a small pattern(Less than 1~2um) like device that can be placed in-die area. (3)"In-die SEM based overlay" shows possibility for high order control of scanner

A methodology to evaluate the memory cell property of STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory) with a CD-SEM (Critical Dimension-Scanning Electron Microscope) was proposed. STTMRAM is one of the promising candidates among various emerging memories, owing to its low power consumption, low latency, and excellent endurance. Meanwhile, the major issues of STT-MRAM are its small resistance window and the etching-induced damage during memory pillar formation process. The resistance variability and the damage region should be minimized to achieve the reliable operation and the size scaling. The correlation analysis between the resistance and the physical dimension was performed. It provided quantitative information required for process development and control, such as the size-independent resistance variability, the width of the damaged region, and the origin of the short failures. They are essential for the investigation of the causes for the cell-to-cell resistance variability as well as for the quantification of the damage during etching process.

In this work, we explore the performances of a low-temperature PEALD technology used to trim/clean/smooth and reshape ArF photoresist lines that could subsequently receive an in-situ spacer deposition required to build up any SAxP grating. Different gas mixtures (O2, N2, H2, Ar and combinations) are evaluated on both blanket and patterned wafers. Trim rate, line profile, surface roughness and chemical modification are characterized using ellipsometry, Fourier transform infrared spectroscopy and atomic force microscopy. The photoresist line roughness is measured from top down SEM imaging and the different contributors to the roughness determined from a Power Spectral Density (PSD) analysis. Few results obtained on EUV photoresist blanket wafers using similar plasma treatments will also be briefly presented.

A methodology to evaluate the electrical contact between nanowire (NW) and source/drain in NW FETs was investigated with SEM voltage contrast (VC). The electrical defects are robustly detected by VC. The validity of the inspection result was verified by transmission electron microscope (TEM) physical observations. Moreover, estimation of the parasitic resistance and capacitance was achieved from the quantitative analysis of VC images, which are acquired with different scan conditions of an electron beam (EB). A model considering the dynamics of EB-induced charging was proposed to calculate the VC. The resistance and capacitance can be determined by comparing the model-based VC with experimentally obtained VC. Quantitative estimation of resistance and capacitance would be valuable not only for more accurate inspection but also for identification of the defect point.

With the continuous shrink in pattern size and increased density, overlay control has become one of the most critical issues in semiconductor manufacturing. Recently, SEM based overlay of AEI (After Etch Inspection) wafer has been used for reference and optimization of optical overlay (both Image Based Overlay (IBO) and Diffraction Based Overlay (DBO)). Overlay measurement at AEI stage contributes monitor and forecast the yield after formation by etch and calibrate optical measurement tools. however those overlay value seems difficult directly for feedback to a scanner. Therefore, there is a clear need to have SEM based overlay measurements of ADI (After Develop Inspection) wafers in order to serve as reference for optical overlay and make necessary corrections before wafers go to etch. Furthermore, to make the corrections as accurate as possible, actual device like feature dimensions need to be measured post ADI. This device size measurement is very unique feature of CDSEM , which can be measured with smaller area. This is currently possible only with the CD-SEM. This device size measurement is very unique feature of CD-SEM , which can be measured with smaller area. In this study, we assess SEM based overlay measurement of ADI and AEI wafer by using a sample from an N10 process flow. First, we demonstrate SEM based overlay performance at AEI by using dual damascene process for Via 0 (V0) and metal 1 (M1) layer. We also discuss the overlay measurements between litho-etch-litho stages of a triple patterned M1 layer and double pattern V0. Second, to illustrate the complexities in image acquisition and measurement we will measure overlay between M1B resist and buried M1A-Hard mask trench. Finally, we will show how high accelerating voltage can detect buried pattern information by BSE (Back Scattering Electron). In this paper we discuss the merits of this method versus standard optical metrology based corrections.

Overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic scanners use high-order corrections or correction per exposure to reduce the residual overlay. It is not enough in traditional feedback of overlay measurement by using ADI wafer because overlay error depends on other process (etching process and film stress, etc.). It needs high accuracy overlay measurement by using AEI wafer. WIS (Wafer Induced Shift) is the main issue for optical overlay, IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). We design dedicated SEM overlay targets for dual damascene process of N10 by i-ArF multi-patterning. The pattern is same as device-pattern locally. Optical overlay tools select segmented pattern to reduce the WIS. However segmentation has limit, especially the via-pattern, for keeping the sensitivity and accuracy. We evaluate difference between the viapattern and relaxed pitch gratings which are similar to optical overlay target at AEI. CDSEM can estimate asymmetry property of target from image of pattern edge. CDSEM can estimate asymmetry property of target from image of pattern edge. We will compare full map of SEM overlay to full map of optical overlay for high order correction ( correctables and residual fingerprints).

A method of sub-nanometer uncertainty for the 3D-profile measurement using TEM (Transmission Electron Microscope) images is proposed to standardize 3D-profile measurement through reference metrology. The proposed method has been validated for profiles of Si lines, photoresist features and advanced-FinFET (Fin-shaped Field-Effect Transistor) features in our previous investigations. However, efficiency of 3D-profile measurement using TEM is limited by measurement time including processing of the sample. In this article, we demonstrate a novel on-wafer 3D-profile metrology as "FIB-to-CDSEM method" with FIB (Focused Ion Beam) slope cut and CD-SEM (Critical Dimension Secondary Electron Microscope) measuring. Using the method, a few micrometer wide on a wafer is coated and cut by 45 degree slope using FIB tool. Then, the wafer is transferred to CD-SEM to measure the cross section image by top down CD-SEM measurement. We apply FIB-to-CDSEM method to CMOS sensor device. 3D-profile and 3D-profile parameters such as top line width and side wall angles of CMOS sensor device are evaluated. The 3D-profile parameters also are measured by TEM images as reference metrology. We compare the 3D-profile parameters by TEM method and FIB-to-CDSEM method. The average values and correlations on the wafer are agreed well between TEM and FIB-to- CDSEM methods.

Line edge roughness (LER) and line width roughness (LWR) are analyzed during pattern transfer in a self-aligned quadruple patterning (SAQP) process. This patterning process leads to a final pitch of 22.5nm, relevant for N7/N5 technologies. Measurements performed by CD SEM (Critical Dimension Scanning Electron Microscope) using different settings in terms of averaging, field of view, and pixel size are compared with reference metrology performed by planar TEM and three-Dimensional Atomic Force Microscope (3D AFM) for each patterning process step in order to investigate the optimal condition for an in-line LWR characterization. Pattern wiggling is als0 quantitatively analyzed during LER/LWR transfer in the SAQP process.

This guest editorial summarizes the Special Section on Control of Integrated Circuit Patterning Variance, Part 3: Pattern Roughness, Local Uniformity, and Stochastic Defects

Two fundamental challenges of line edge roughness (LER) metrology are to provide complete and accurate measurement of LER. We focus on recent advances concerning both challenges inspired by mathematical and computational methods. Regarding the challenge of completeness: (a) we elaborate on the multifractal analysis of LER, which decomposes the scaling behavior of edge undulations into a spectrum of fractal dimensions similarly to what a power spectral density (PSD) does in the frequency domain. Emphasis is given on the physical meaning of the multifractal spectrum and its sensitivity to pattern transfer and etching; (b) we present metrics and methods for the quantification of cross-line (interfeature) correlations between the roughness of edges belonging to the same and nearby lines. We will apply these metrics to quantify the correlations in a self-aligned quadruple patterning lithography. Regarding the challenge of accuracy, we present a PSD-based method for a noise-reduced (sometimes called unbiased) LER metrology and validate it through the analysis of synthesized SEM images. Furthermore, the method is extended to the use of the height–height correlation functions to deliver noise-reduced estimation of the correlation length and the roughness exponent of LER.

A method for the inline measurement of the tunnel oxide–nitride-blocking oxide (ONO) film thickness in 3D-NAND devices was studied. The ONO film, whose thickness is critical to the device properties, cannot be measured with conventional methods because it is deposited on the sidewall of a memory hole. Thus, a method to measure the thickness of this vertical film is required. We propose a critical dimension-scanning electron microscope (CD-SEM) measurement. The film thickness can be obtained by measuring the hole diameter before and after the film deposition. Namely, the decrease in the hole diameter should be twice of the thickness in principle. However, its applicability to the actual 10-nm-thick ONO film has not been verified. In this study, the measurement precision and the validity of the method were examined with actual ONO film in the 3D-NAND test wafers. The results showed excellent precision (0.08 nm) and good consistency with planar transmission electron microscope (TEM) and ellipsometry results. In addition, the method revealed the subnanometer thickness difference depending on the nominal hole diameter and the hole density. It suggests the impact of inhomogeneity in the source gas supply during the film deposition. These results ensure that the method is sufficiently precise for the inline local thickness measurement of the ONO film. With this method, yield and reliability managements in the 3D-NAND device manufacturing would be improved.