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This study observes the MOSFET's performance concerning several biomolecules for use as a biosensor device. The double gate MOSFET with gate stack configuration has been chosen as the suggested device to surpass the limitations of short-channel effects (SCEs). The cavity was created to restrict the passage of charged and uncharged biological molecules so that they could be detected. These molecules fill the cavity, changing the device's electrical properties. The Double Gate MOSFET (DG-MOSFET) biosensor is subject to limitations such as Short Channel Effects (SCEs) and issues with the power supply. The suggested device decreased SCEs and it also demonstrates the potential benefits of having DG-MOSFETs with gate stacking for biosensor applications. Comparison of transconductance, the generating factor for transconductance, and sensitivity parameters such as Id and Vth sensitivity and Ion/Ioff sensitivity has been carried out in this study.Article Highlights: The variation of temperature can influence the mobility of charge carriers within the semiconductor, affecting the conductance of the sensor. Depending on the specific biomolecule being detected, changes in temperature can modulate the interaction between the biomolecule and the sensor surface, leading to alterations in the electrical properties of the device and these changes can be precisely measured, thereby enhancing the sensitivity of detection. By systematically varying the temperature, researchers can explore the thermodynamic and kinetic aspects of the binding events, allowing for fine-tuning of the sensor performance to meet specific application requirements. [ABSTRACT FROM AUTHOR]

The design and analysis of a gate stack gate-all-around junctionless nanowire field-effect transistor (GAA-JL-NWFET) with a catalytic metal as gate contact for oxygen gas sensing is presented in this study. An n-channel GAA-JL-NWFET design using gold (Au) as the gate metal electrode is employed for oxygen sensing by utilizing appropriate work function values, which interact with oxygen gas and change the device's electrical properties. This work focuses on changes in temperature (300–500 K) and Au metal gate work function (5.05–5.20 eV) to investigate the presence of oxygen molecules and their impact on the GAA-JL-NWFET gas sensor performance. Changes in the surface potential, threshold voltage, hole concentration, electron concentration, subthreshold voltage, electric field, and drain current using the ATLAS TCAD simulator are investigated for the adsorption of gas molecules to determine the electrical characteristics of the proposed device. Changes in threshold voltage (Vth), switching ratio, and subthreshold current sensitivity ( S I OFF ) can be considered as sensitivity parameters for sensing oxygen gas molecules. The results reveal that as the Au work function shifts at the gate by 100 mV, the sensitivity ( S I OFF ) enhancement using gate stack GAA-JL-NWFET-based oxygen gas sensors compared to GAA-MOSFET and conventional MOSFET are 15.13% and 88.31%, respectively. Based on our simulation results, the proposed device offers excellent sensitivity, low power consumption, and a fast response time, making it an appropriate candidate for oxygen gas sensing, including environmental monitoring, medical diagnosis, and industrial safety. [ABSTRACT FROM AUTHOR]

By understanding the potential benefits of Gate Stack Dual Material double gate MOSFET (DG MOSFET), this research aims to contribute to the investigation of its electrical characteristics with improved performance and dependability. A detailed investigation is conducted into the temperature dependent electrical properties at different temperatures. A detailed analysis is conducted on the enhanced gate controllability in lower technology nodes and the protection against short channel effects. Together with the DC performances, this research also analyzes the suggested device's analog performance. The device's performance matrix was presented for temperatures ranging from 70 K to 800 K. The results showsthe improvement the drain current, transconductance, and transconductance generation factor(TGF) with decrease in temperature.

The goal of this work was to study nitrogen implantation from plasma with the aim of applying it in dual gate oxide technology and to examine the influence of the rf power of plasma and that of oxidation type. The obtained structures were examined by means of ellipsometry, SIMS and electrical characterization methods.

Experiments presented in this work are a summary of the study that examines the possibility of fabrication of oxynitride layers for Si structures by nitrogen implantation from rf plasma only or nitrogen implantation from rf plasma followed immediately by plasma oxidation process. The obtained layers were characterized by means of: ellipsometry, XPS and ULE-SIMS. The results of electrical characterization of NMOS Al-gate test structures fabricated with the investigated layers used as gate dielectric, are also discussed.

This work demonstrates the simulation analysis of a novel device Plasma-Assisted Dual-Material Stacked Gate-Oxide Carbon Nanotube Field Effect Transistor (DM-SGCNFET) with a stacked gate oxide structure consisting of two oxides - SiO2 and HfO2. The performance metric of the simulated device is compared with a SiO2 based similar device (DM-CNFET) for varying sets of plasma parameters that corresponds to different values of channel length. Both the devices feature a PECVD grown vertically aligned semiconducting carbon nanotube implemented as the channel material. The comprehensive analysis delineates that the DM-SGCNFET offers enhanced values of drain current, transconductance, output conductance, early voltage, gain, gate capacitance, better switching ratio, and reduced channel resistance as compared to DM-CNFET. The novel structure contemplating a dual-material gate and a high-k dielectric gate stack in CNT based transistors warrants as an appropriate device for digital and analog applications providing high efficiency. The paper further explores the DM-SGCNFET device for linearity distortion performance by evaluating gm2, gm3, VIP2, VIP3, IIP3, IMD3 and 1-dB compression point for altering values of plasma parameters. [ABSTRACT FROM AUTHOR]

Germanium (Ge) and germanium tin (GeSn) are strong candidate materials for novel electronic device such as spin MOS field-effect transistor (FET) or flexible devices. A high-quality insulating layer on Ge(Sn) should be formed at low temperatures to realize these applications. In this study, we fabricated a Ge MOS capacitor (CAP) and n-MOSFET with a SiO 2 /GeO 2 gate dielectric using an electron cyclotron resonance plasma process and subsequent post-deposition annealing at a low temperature of 210 °C. The MOSCAPs show the typical electrical characteristics without significant degradation compared with the samples fabricated at a higher temperature of 450 °C. The n-MOSFET shows distinct output characteristics with clear saturation behavior and high current drivability. From the flatband voltage comparison among different annealing temperatures, high-temperature annealing induces the interface dipole formation in the gate insulator, significantly shifting flatband voltage to a negative direction. X-ray photoelectron spectroscopy analysis suggests that the origin of the interface dipole is oxygen atom movement at a SiO 2 /GeO 2 interface. This information will be an important guideline for fabricating a high-quality insulator on Ge(Sn) at low temperatures. [ABSTRACT FROM AUTHOR]

In this paper the performance of gate stack metal oxide semiconductor field effect transistor (MOSFET) is investigated with respect to different bio molecules for application as biosensor device. In order to beat the limits of short channel effects (SCEs) the double gate stack MOSFET has been preferred as the proposed device. For biosensor application, dielectric modulation technique has been chosen and effect of different bio molecules like protein, biotin, streptavidin, APTES, etc. are studied to verify the sensitivity as a biosensor for this proposed device. The sensitivity parameter and analog/Rf parameter have been studied for different bio-molecules and a comparative result has been established. The sensitivity of bimolecules located in the cavity side by the oxide region is observed in the variation of threshold voltage and also different analog and RF parameters which can be used for future application in the area of medical science. Two oxide layer one is high k(HfO2) and low k(SiO2) has been used for stacking. For simulations, 2D Sentrausu TCAD simulator has been used. [ABSTRACT FROM AUTHOR]

This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson's equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29 % improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool. [ABSTRACT FROM AUTHOR]

We fabricated n-channel MOSFETs with various gate dielectrics on (111) oriented 3C-SiC/Si. Fabricated MOSFETs operated as inversion mode devices successfully. The MOSFET with sputter-deposited SiO2/plasma oxidized interlayer showed a high peak field-effect mobility of 131 cm2 Vâˆ'1 sâˆ'1. The gate stack can be formed at a low temperature of 400 °C, which means the process is absolved from high-temperature thermal oxidation for a gate stack. The detailed analysis of charges and traps in the gate stacks clarified that Coulomb scattering is well-suppressed in the inversion channel. These results will be the first step for a high-performance 3C-SiC application, including on-chip hetero-integrated electronic devices. [ABSTRACT FROM AUTHOR]

In this work, we experimentally explore and compare FET gate stacks with and without an inner metal plane between a linear dielectric (SiO2) and a ferroelectric layer (Si-doped HfO2) operating in the negative capacitance (NC) regime. The use of nanosecond-range pulses enables us to observe hysteresis-free NC and reconstruct the ${S}$ -shaped polarization-voltage curves. The devices with the inner metal plate show a higher equivalent NC value, which offers the potential for a higher differential amplification in a NC-FET. However, such a NC region is observed over a smaller range of electric field and polarization, which leads to hysteresis. Moreover, the presence of a metal layer in between the ferroelectric and the insulator favors domain formation resulting in destabilization of the NC effect. For the gate structure where the ferroelectric and the insulator are in contact, the ${S}$ -shaped polarization-voltage curve shows a better agreement with Landau–Ginzburg–Devonshire formalism for the monodomain state. The uniform polarization closely mimicking the monodomain state is possible due to the polarization imprint occurring due to the structural asymmetry. By nanometer resolution polarization mapping via off-resonance piezoelectric force microscopy (PFM), we corroborate the presence of imprint, which can intrinsically stabilize one ferroelectric state. Overall, the article provides an experimental demonstration that the absence of the inner metal plane in the gate structures stabilizes the NC regime favorable for hysteresis-free NC-FET. [ABSTRACT FROM AUTHOR]

In this Paper, we have studied and compared the performance of two different configurations of simulation model advanced MOSFET devices which can be used for biosensor application. The bio-molecules like protein, biotin, streptavidin, APTES, etc., undergo label free electrical detection with the help of dielectrical modulation technique in order to overcome the limitations of short channel effect in a more efficient way. The bio-molecules trapped inside the cavity region change the electrical parameters of the MOSFET. Biosensors based on MOSFETs have certain issues, like short channel effects (SCEs) and problems related to scaling and power supply. Therefore the proposed device is better withstand to SCEs and can be consider as an alternative for biosensing applications. For channel material, silicon is used for both the configurations i.e. with stack and without stack model and we have also studied the performance of the device based on the analog as well as RF parameters by considering the protein as bio-molecule in the cavity. Two different oxide materials are used to design the device structure such as HfO2 (K = 25) and SiO2 (K = 3.9) and for simulation purpose the 2D Sentrausu TCAD simulator has been used. The sensing capability of this proposed dielectric modulated device can be applicable for IOT based applications. They can also be uses in health IOT systems for medical research applications and as bio chip sensor in wearable device so as to study the protein content of the human body. [ABSTRACT FROM AUTHOR]

Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers, thus eventually improving drain current and trans-conductance of the device. In this work, the speed of operation for DG MOSFET is improved by reducing the channel length where dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects. In the presented device, the metal closer to the source and drain has higher and lower work function, respectively which causes a significant decrement in the peak electric field at the drain side and so the SCEs. The carrier mobility is also increased due to enhanced electric field in the channel, near the source, caused by higher work function gate material which, in turn, increases the MOSFET's driving current. The screening effect reducing SCEs and an increment in the acceleration of the charge carriers in the channel are mainly attributed due to higher and lower threshold voltage found near the source and drain, respectively. [ABSTRACT FROM AUTHOR]

We have examined impacts of gate insulator (Al2O3 or HfO2) and gate electrode (TiN or W) on electrical performance of ZnSnO/Si bilayer tunneling field-effect transistors (TFETs). It is found from the capacitance-voltage (C-V) characteristics that the W gate is effective to reduce the counter-clockwise hysteresis. Additionally, the optimal temperature of post-metallization annealing (PMA) is different for each gate stack, and this optimization is critically important for the high ON-state current (ION) and steep ON/OFF switching. The W/Al2O3/ZnSnO/Si bilayer TFET provides the hysteresis-free steep ON/OFF switching with the minimum sub-threshold swing (SS) of 65.4 mV/dec. and average SS of 72.0 mV/dec. in a gate-voltage swing of 0.3 V, which are 19% and 18% lower than the control TiN/Al2O3/ZnSnO/Si bilayer TFET. When the gate stack is replaced by W/HfO2/Al2O3, the TFET exhibits less steep ON/OFF switching in spite of thinning capacitance equivalent thickness (CET) from 5.9 and 2.3 nm. These results indicate the importance of improvement in the gate stack quality on the sub-threshold characteristics of the bilayer TFETs.

In this paper, the proposed architecture of electrostatic doped based nanotube tunnel field-effect transistor (NT-TFET) has been discussed. The proposed architecture of NT-TFET structure showed improved performance as compared to nanowire TFET (NW-TFET) with the same physical parameters. To analyze the performance of electrostatic doped based NT-TFET, different parameters like device parameter, analog parameter and linearity parameter have been discussed. Electron/hole concentration, electric field, electric potential, energy band diagram and non-local band-to-band tunneling rate (BTBT) have been analyzed as several device parameters. The tunneling rate and tunneling area are greater in NT-TFET as compare to NW-TFET. Analog parameters include drain current, ON-current (ION), OFF-current (IOFF), ION/IOFF, intrinsic gain, output conductance, sub-threshold slope, and threshold voltage have been analyzed. The Drain current (IDS) of value 3*10−5 A/μm, OFF-current is of the order of ~ 10−19 and higher ION/IOFF current ratio of 2*1012 are obtained. The proposed architecture of electrostatic doped based nanotube TFET (NT-TFET) has improved the drain current, steep sub-threshold, OFF-current, and ION/IOFF current ratio. [ABSTRACT FROM AUTHOR]

• The effect of ITC on electrical parameters of GSHJ-SOITFET and GSHJ-STFET are highlighted. • I ON /I OFF ratio is found in the order of 107 for both the devices. • IMD3 is lower in GSHJ-TFET indicates improved linearity behaviour. In this work, the influence of interface trap charges (ITCs) on electrical parameters of gate stacked heterojunction silicon on insulator Tunnel FET (GSHJ-SOITFET) and GSHJ-TFET on SELBOX substrate (GSHJ-STFET) is investigated using TCAD simulator. Here, two types of trap distributions like Uniform and Gaussian are considered at Silicon/gate oxide interface. The influence of ITCs on transfer characteristic, electron density, energy band diagram (ON, OFF and Ambipolar states), transconductance (g m), and cut-off frequency (f t) are highlighted for these two structures. Moreover, the linearity parameters are highlighted in the presence of ITCs of these structures. It is seen that DC, RF/analog, and linearity characteristics of GSHJ-STFET are immune to ITCs compared to GSHJ-SOITFET. Also, GSHJ-STFET has improved electrical behavior than GSHJ-SOITFET. The proposed fabrication processing steps of GSHJ-STFET is also highlighted in this work. Finally, a comparative study of electrical parameters for GSHJ-STFET with the existing literature is highlighted. [ABSTRACT FROM AUTHOR]

A dopingless multi-gate inverted-T Shape device has been proposed with Schottky source/drain contacts. Gate oxide engineering is performed on the proposed device, and its two configurations namely Hetero-Dielectric (HD) and Gate-Stack (GS) are implemented. The proposed HD configuration of dopingless inverted-T shape FET has asymmetric oxide; where oxide (Hf x Ti 1-x O 2) having high value of dielectric is placed on source side and SiO 2 with lower dielectric value is placed on drain side. The designed device showcase a leakage current of approximately 10 − 16 A in contrast to the traditional junctionless FET which has leakage of 10−10 A. Also, comparative analysis of the GS and HD dopingless multi-gate inverted-T shape transistor is outlined at different parameters including channel length, fin width and Ultra-thin body thickness. AC analysis of the device has been done to evaluate cut-off frequency and gain bandwidth product. Additionally, p-channel configuration is formulated in conjunction with n-channel MOS configuration to investigate the device's suitability for applications employing CMOS technology. [ABSTRACT FROM AUTHOR]

This paper examines the DC performance of Dual-Gate MISHEMT with different substrate material such as sapphire, silicon carbide SiC, and silicon. The performance parameters evaluated are threshold voltage, drain current, transconductance, and drain conductance. It is observed that DG-MISHEMT with the sapphire substrate and HfO2 gate dielectric results in positive threshold voltage shift from −4.7 to −3.8 V(∼19%) and also degrades the drain current as compared to the device with silicon nitride gate dielectric due to the reduced channel charge concentration. But the device with HfO2/Al2O3 gate stack maintains 182 mA/mm of IDS along with a positive threshold voltage shift of 14.8% as compared to DG-MISHEMT with Si3N4 gate dielectric and sapphire substrate. A similar performance has been observed with Dual-Gate MISHEMT with SiC and silicon substrate. The device, having the silicon substrate and HfO2/Al2O3 gate stack, shows a positive threshold voltage shift of ∼53%, but as a trade-off the drain current reduces to 158 mA/mm as compared to 183 mA/mm of the device at low drain bias with the sapphire substrate and Si3N4 gate dielectric. [ABSTRACT FROM AUTHOR]

In this investigation, extensive simulations were performed for an AlGaN/GaN Dual-Gate MISHEMT configuration using ATLAS TCAD to optimize the device design for high power switching applications. We conducted a simulation study for the breakdown characteristics of a Dual-Gate AlGaN/GaN (DG)-MISHEMT with different gate lengths as explained in this paper. The optimized device with 0.25 µm gate length exhibits an breakdown voltage > 700 V and an cut-off frequency of 50 GHz when gate2 (G2) is attached to the source and bias is applied at gate1 (G1). We studied the impact on a breakdown characteristics and the frequency performance of different dimensions such as distance between the two gates (LGG), gate1-to-source distance (LG1S) and gate1-to-drain distance (LG1D). The optimized device design was further used to study the scattering-parameters for different gate combinations. Further improvement in breakdown voltage and Johnson's figure of merit (fT × VBR) is achieved for the DG-MISHEMT with HfO2–Al2O3 as gate insulator. [ABSTRACT FROM AUTHOR]

In this present study, junctionless vertical tunnel field-effect transistor (JL-VTFET) with catalytic metals as gate contacts is proposed for gas sensing applications. The vertical double-sided gate architecture provides better gate controllability over conventional TFETs for band-to-band tunneling (BTBT). An architecture for n-channel JL-VTFET with Palladium (Pd) as gate metal is analyzed for Hydrogen sensing, while Cobalt (Co) and Molybdenum (Mo) metals as gate contacts are analyzed for Ammonia sensing. P + pockets are created near the source region by using work function values befitting the aforementioned catalytic metals. Characteristics of the proposed structure are studied considering the electric field, surface potential, and energy bandgap graphs concerning adsorption of gas molecules, using Silvaco ATLAS TCAD simulator. Simulation results of JL-VTFET with 50-nm gate length show good sensitivity calibrations (SIdoff ~ 1.99 × 103, 2.09 × 103 and 6.43 × 102) and high Idon/Idoff ratio (~ 4.3 × 109, ~ 2.01 × 107 and 1.33 × 1012) for Co, Mo and Pd as gate metals, respectively [ABSTRACT FROM AUTHOR]

This article presents a comparative low-frequency noise (LFN) characterization of gate-all-around nanosheet n-channel Si metal–oxide–semiconductor field effect transistors, processed with three different metal gates (MGs): an aluminum-based reference process and two alternative effective work function (EWF) stacks. In all cases, the gate dielectric is composed of HfO2 over an SiO2 interfacial layer. The LFN figures of merit are extracted, such as the oxide trap density and Coulomb scattering coefficient, and the correlations with the threshold voltage and the electron mobility are investigated. Carrier number fluctuations are confirmed as the dominant mechanism of the 1/ƒ noise for all evaluated devices. Additionally, it is shown that the specific MG can contribute to the carrier scattering, degrading the electron mobility. The most promising results are obtained for one of the alternative MGs, exhibiting a low oxide trap density level, a low threshold voltage and insignificant mobility degradation. [ABSTRACT FROM AUTHOR]

This paper proposes a 2-D analytical model developed for Double Gate Junctionless Transistor with a SiO2/HfO2 stacked oxide structure. The model is solved by Poisson's equation using the variable separation method. The proposed model gives analytical expressions for electrostatic potential distribution, threshold voltage and drain current with the effects of depletion regions at source/drain side. Furthermore, the potential and drain current models are used to evaluate the Short Channel Effects (SCEs) of the proposed device. The electrical characteristics and SCEs are analyzed by different possible definitions of channel length, silicon thickness, equivalent oxide thickness, and depletion length variations. The developed model results are validated through comparison with Sentarus TCAD simulator results. In addition, the proposed device is also studied for the digital circuit performance of CMOS inverter circuit by the voltage transfer characteristics, transient analysis, and AC small signal analysis. [ABSTRACT FROM AUTHOR]

In this paper, we have incorporated the novel concept of gate material engineering in a three-dimensional tri-gate TFET structure with SiO2/HfO2-stacked gate oxide to reap the dual benefits of triple gate material and dielectric engineering in a single device. A detailed 3D analytical modeling of electrostatic potential distribution and electric field of the proposed structure is developed here solving 3D Poisson's equation with suitable boundary conditions. Tunneling current is then extracted by integrating the band-to-band tunneling generation rate over the volume of the device. A comprehensive performance analysis of the present structure is analyzed in terms of potential profile, electric field and ON-current characteristics of the device by varying several parameters such as channel length, channel thickness, oxide thickness, applied gate and drain bias voltages. An overall performance comparison of the proposed structure with dual and single gate material equivalent tri-gate TFET structures with and without high-k gate stack is also demonstrated to explore the functional efficiency of the present structure. The results of the derived analytical model are compared with SILVACO ATLAS simulated data verifying the accuracy of our model in order to validate it for establishing the superiority of the structure. [ABSTRACT FROM AUTHOR]

We show electrical properties of a Ge-based top-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structure with epitaxial ferromagnetic Heusler alloy/Ge Schottky-tunnel contacts, fabricated with a low-temperature gate-stack process. For shaping the Ge-MOSFET with the ferromagnetic source and drain (S/D) contacts, we use a combination process of Ar+ ion milling and reactive ion etching (RIE). As a consequence of the formation of a gate stack (SiO 2 /GeO 2) using a process temperature of 240 °C, we demonstrate inversion channel MOSFETs with a low gate-voltage operation (V G ∼5 V). Furthermore, we achieve a relatively high field-effect mobility (μ FE) of ∼300 cm2/Vs compared to those in a Si-based back-gate spin-MOSFET reported previously [Phys. Rev. B 102 , 035305 (2020).]. This study will open a way for developing a Ge-based top-gate spin-MOSFET on the Si platform. [ABSTRACT FROM AUTHOR]

A high-quality insulating film on germanium is essential for germanium applications. In this study, we oxidized metal yttrium at 500–550 °C to generate an yttrium oxide (Y-oxide) layer on germanium. According to transmission electron microscopy images, Y-oxide comprised three layers, which were Y 2 O 3 , YGeO 3 , and GeO x from the top side. n-Type metal-oxide-semiconductor (n-MOS) capacitors and n-type MOS field-effect transistors (n-MOSFETs) with the Y-oxide gate insulator showed typical electrical characteristics. The n-MOS capacitor with the Y-oxide gate insulator had a lower interface state density (D it) and border trap density (N bt) than the n-MOS capacitor with a thermally oxidized GeO x insulator, suggesting that defects were terminated by Y atoms in the GeO x layer and GeO x /Ge interface. In contrast, the D it –energy distribution and N bt temperature dependence of the Y-oxide gate insulator were similar to those of the GeO x gate insulator, indicating that the defect signals originated in GeO x underlying YGeO 3. The structural analysis showed that the temperature of metal yttrium oxidation affected only the GeO x thickness. Therefore, adjusting the conditions of metal yttrium oxidation may produce Y-oxidized gate stacks with a thinner GeO x layer or even direct contact of YGeO 3 and Ge, which may result in different D it values, N bt values, and N bt –temperature trends. [ABSTRACT FROM AUTHOR]

This paper proposes a gate-all-around silicon nanowire dopingless field-effect transistor (FET), utilizing a gate-stacked technique. The source and drain regions are formed by employing a charge plasma concept, with the application of appropriate work functions for metal contacts. The charge plasma approach reduces the need for doping control during fabrication, and thus reduces the thermal budget, while the gate-stacked structure solves the problem of scaling limitations with respect to the SiO2 dielectric thickness (< 2 nm). The simulation results show that the proposed device, when compared with a conventional junctionless nanowire FET (JL-NWFET), possesses enhanced performance parameters, with improved immunity to short-channel effects. The random dopant fluctuations (RDFs) of the proposed device are analyzed and compared with those of a conventional JL-NWFET. The conventional device has a high doping concentration, and as a result suffers from higher RDFs, whereas the proposed dopingless device possesses lower RDFs. The process parameters used to measure sensitivity to RDFs include the radius, doping concentration and gate oxide thickness. When the radius of the nanowire is varied by + 30%, changes in threshold voltage, on-state current and subthreshold slope of 66, 63 and 12%, respectively, are observed in the JL-NWFET, versus 5, 22.6 and 1.8% for the proposed dopingless device (CP-NWFET). Similar variations in doping concentration and gate oxide thickness are seen with the JL-NWFET, whereas the CP-NWFET is largely unaffected. Thus, the proposed gate-stacked dopingless CP-NWFET solves the issue of both doping control and scaling limitation of the gate oxide layer, which paves the way for easier fabrication, with exceptional immunity against parametric variations, making it a good candidate for future nanoscale devices. [ABSTRACT FROM AUTHOR]

In this work, gate-stack based junctionless Si-nanotube (JLSiNT) FET is studied to investigate the effect of high- K gate dielectric material in-conjunction with interfacial layer thickness (T I ) and outer gate length (L g ) on analog/RF figures of merit (FOM) of the device. With the use of high- K gate dielectric intrinsic dc gain (A V ), cut-off frequency (f T ), and maximum oscillation frequency (f MAX ) degrades. It is observed that the degradation in analog/RF performance when high- K gate dielectrics are used, can be improved by taking higher T I . Furthermore, it is also observed that by using optimal T I (0.7 nm), the variation in ΔA V (A V( K =3.9) - A V( K =40) ), Δf T (f T( K =3.9) – f T( K =40) ), and Δf MAX (f MAX( K =3.9) – f MAX( K =40) ) FOMs are almost invariant when outer gate length (L g ) is scaled down from 30 nm to 15 nm. Therefore, it is pertinent to consider higher interfacial layer thickness (~0.7 nm) and lower outer gate length (~ 15 nm) while designing gate-stack based JLSiNT-FET for analog/RF applications. [ABSTRACT FROM AUTHOR]

This paper investigates the performance of 6 T SRAM cell using high- K gate dielectric based junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high- K gate dielectric enhances the delay performance of the JLSiNTFET based 6 T SRAM cell. Read access time (RAT) and write access time (WAT) improves by ∼18% and ∼20% when TiO 2 is used as gate dielectric instead of SiO 2 . The hold, read, and write SNMs (static noise margin) of the 6 T SRAM cell also improves marginally by the use of high- K gate dielectric. Furthermore, it is also observed that the improvement in hold SNM (HSNM), read SNM (RSNM), and write SNM (WSNM) can be boosted by using higher interfacial layer thickness (T I ). However, the improvement in read access times (RAT) & write access time (WAT) degrades at higher T I . Thus, high- K gate dielectrics with high interfacial layer thickness are more suitable for JLSiNT-FET based 6 T SRAM cell. [ABSTRACT FROM AUTHOR]

In this paper, the effect of channel parameters like channel thickness (T Si ) and channel length (L g ) on the analog/RF performance of high- K gate-stack based junctionless Trigate-FinFET (JLT-FinFET) have been studied using TCAD mixed-mode Sentaurus device simulator. It is observed that use of high- K gate dielectric deteriorates the analog/RF performance of the gate-stack based JLT-FinFET. The variation of change in analog/RF FOMs (ΔFOM = FOM K =3.9 - FOM K =40 ) with respect to channel parameters have been focused throughout this study. It is observed that the deterioration in intrinsic dc gain (ΔA V = (A V( K =3.9) - A V( K =40) )) with high- K gate dielectrics aggravates with scaling down of T Si (from 2.31 dB at T Si = 12 nm to 5.2 dB at T Si = 6 nm) but increases marginally with scaling down of L g (ΔA V = 7.6 dB at L g = 30 nm and ΔA V = 8.7 dB at L g = 15 nm). However, the deterioration in maximum oscillation frequency (Δf MAX ) and cut-off frequency (Δf T ) are almost negligible. Moreover, it is also observed that the deterioration in analog/RF FOMs due to high- K gate dielectrics can be reduced by upscaling of interfacial layer thickness (T I ). Consequently, higher T I value can be convenient in designing of high -K gate-stack based junctionless Trigate-FinFET at lower T Si for analog/RF applications. [ABSTRACT FROM AUTHOR]

In this paper, we present comprehensive results on Al-postmetallization annealing (Al-PMA) effect for the SiO 2 /GeO 2 gate stack on a Ge substrate, which were fabricated by a physical vapor deposition method. The effective oxide thickness of metal-oxide-semiconductor (MOS) capacitor (CAP) was ~7 nm, and the Al-PMA was performed at a temperature in the range of 300–400 °C. The flat band voltage ( V FB ), the hysteresis (HT), the interfacial states density ( D it ), and the border traps density ( D bt ) for MOSCAPs were characterized by a capacitance–voltage method and a constant-temperature deep-level transient spectroscopy method. The MOSCAP without Al-PMA had an electrical dipole of ~−0.8 eV at a SiO 2 /GeO 2 interface, which was disappeared after Al-PMA at 300 °C. The HT, D it , and D bt were decreased after Al-PMA at 300 °C and were maintained in the temperature range of 300–400 °C. On the other hand, the V FB was monotonically shifted in the positive direction with an increase in PMA temperature, suggesting the generation of negatively charged atoms. Structural analyses for MOSCAPs without and with Al-PMA were performed by a time-of-flight secondary ion mass spectroscopy method and an X-ray photoelectron spectroscopy method. It was confirmed that Al atoms diffused from an Al electrode to a SiO 2 film and reacted with GeO 2 . The dipole disappearance after Al-PMA at 300 °C is likely to be associated with the structural change at the SiO 2 /GeO 2 interface. We also present the device performances of Al-gated p-channel MOS field-effect transistors (FET) with PMA treatments, which were fabricated using PtGe/Ge contacts as source/drain. The peak field-effect mobility ( μ h ) of the p-MOSFET was reached a value of 468 cm 2 /Vs after Al-PMA at 325 °C. The μ h enhancement was explained by a decrease in the total charge densities at/near the GeO 2 /Ge interface. [ABSTRACT FROM AUTHOR]

The accurate characterization of nanolayered systems is an essential topic for today’s developments in many fields of material research. Thin high-k layers and gate stacks are technologically required for the design of current and future electronic devices and can be deposited, e.g., by Atomic Layer Deposition (ALD). However, the metrological challenges to characterize such systems demand further development of analytical techniques. Reference-free Grazing Incidence X-ray Fluorescence (GIXRF) based on synchrotron radiation can significantly contribute to the characterization of such nanolayered systems. GIXRF takes advantage of the incident angle dependence of XRF, in particular below the substrate’s critical angle where changes in the X-ray Standing Wave field (XSW) intensity influence the angular intensity profile. The reliable modeling of the XSW in conjunction with the radiometrically calibrated instrumentation at the PTB allows for reference-free, fundamental parameter-based quantitative analysis. This approach is very well suited for the characterization of nanoscaled materials, especially when no reference samples with sufficient quality are available. The capabilities of this method are demonstrated by means of two systems for transistor gate stacks, i.e., Al2O3 high-k layers grown on Si or Si/SiO2 and Sc2O3 layers on InGaAs/InP substrates.

The performance of strained silicon (Si) as the channel material for today’s metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.