Search

A new gate driver with metal oxide thin‐film transistors (MO‐TFTs) has been presented for micro‐light‐emitting diode (Micro‐LED) display. The proposed gate driver employing linearly decreasing sweep signal generated module could realize the line‐by‐line pulse width modulation (PWM) driving method, which is valuable for application in high‐resolution Micro‐LED display compared with the conventional driving method employing global sweep signal. A simple Micro‐LED pixel circuit including an inverter module driven by the analog PWM method is employed to demonstrate the feasibility of the proposed gate driver. A 10 × 10 green Micro‐LED display array has been fabricated with MO‐TFTs backplane technology. It is shown that a 10‐μs width pulse and linearly scanning sweep signal can be successfully output. Consequently, the pixel circuit array can be driven properly under analog line‐by‐line PWM driving method. [ABSTRACT FROM AUTHOR]

Various methods have been discussed in the literature regarding enabling the over-current (OC) capability of silicon carbide (SiC) MOSFETs. SiC MOSFETs can operate at up to 250 °C without failure. One of their features is to permit transient operation at elevated temperatures. This is possible if the stress on the gate oxide and packaging can be kept to a level that can be handled. This paper, instead, investigates the potential of enabling the OC capability of SiC MOSFETs by modifying the gate-source voltage. Since the on-state resistance ( R D S (o n) ) of SiC MOSFETs decreases with an increase in the gate voltage ( V G S ), the conduction losses can be decreased by increasing the V G S . Experiments and simulations have been performed to predict the R D S (o n) with the increase in V G S . It is found that the simulation models provided by manufacturers can be used to predict R D S (o n) accurately even outside the specifications, hence facilitating the precise estimation of conduction losses. It is also concluded that V G S can be increased during OCs in order to keep the conduction losses within the safety limits. A simple concept for implementing this function on a gate driver is also proposed with the additional functionality of increasing the V G S during OC by measuring the on-state voltage of the MOSFET. [ABSTRACT FROM AUTHOR]

With the increasing demand for high power density, and to meet extreme working conditions, research has been focused on investigating the performance of power electronics devices at cryogenic temperatures. The aim of this paper is to review the performance of power semiconductor devices, passive components, gate drivers, sensors, and eventually power electronics converters at cryogenic temperatures. By comparing the physical properties of semiconductor materials and the electrical performance of commercial power semiconductor devices, silicon carbide switches show obvious disadvantages due to the increased on-resistance and switching time at cryogenic temperature. In contrast, silicon and gallium nitride devices exhibit improved performance when temperature is decreased. The performance ceiling of power semiconductor devices can be influenced by gate drivers, within which the commercial alternatives show deteriorated performance at cryogenic temperature compared to room temperature. Moreover, options for voltage and current sense in cryogenic environments are justified. Based on the cryogenic performance of the various components afore-discussed, this paper ends by presenting an overview of the published converter, which are either partially or fully tested in a cryogenic environment.

This paper presents a high-frequency (HF) magnetic pulse generator designed for low-intensity transcranial magnetic stimulation (LI-TMS) applications. HF pulse stimulation can induce a strong electric field with minimal current and enhance the penetration depth of the electric field in human tissue. The HF magnetic pulse generator was designed and fabricated using a microcontroller unit, gate driver, full-bridge coil driver, and stimulation coil. Measurements with a full-bridge circuit supply voltage of 10 V demonstrated an electric field intensity of 6.8 Vpp/m at a frequency of 1 MHz with a power dissipation of 2.45 W. Achieving a similar electric field intensity at a frequency of 100 kHz required approximately ten times the coil current. Additionally, a quasi-resonant LC load was introduced by connecting a capacitor in series with the stimulation coil, which set the resonant frequency to approximately 10% higher than the frequency of 1 MHz. This approach reduced the coil impedance, achieving higher current with the same bias supply voltage. Experimental results showed an enhanced electric field intensity of 19.1 Vpp/m with a supply voltage of only 1.8 V and reduced power dissipation of 1.11 W. The proposed HF pulse train with quasi-resonant coil system is expected to enable a low-power LI-TMS system. [ABSTRACT FROM AUTHOR]

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control. [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN) devices switch faster than silicon devices, making them more vulnerable to significant switching oscillations. To reduce the effect of crosstalk in GaN High Electron Mobility Transistor (GaN HEMT)-based bridges, this paper introduces a passive clamp circuit to restrain gate source voltage oscillations. Utilizing resistive and capacitive diodes, as well as diodes and transistors, a bootstrap driving circuit can be established. This circuit forms a low impedance Miller current path from the driving IC to the GaN device, which decreases the impact of both positive and negative crosstalk. Employing resistive and capacitive diodes, as well as diodes and transistors, a bootstrap driving circuit can be established. This circuit creates a low impedance Miller current path from the driving IC to the GaN device, reducing the effects of the positive and negative crosstalk. This method, which mostly uses passive components, simplifies the circuit design in comparison to other passive gate driver methods. Through dual-pulse testing with a GS661008P, its capacity to suppress positive and negative crosstalk in GaN devices has been confirmed. [ABSTRACT FROM AUTHOR]

Recently there is an increasingly high demand for OLED (organic light‐emitting diode) panel to develop corresponding shift register driver circuits for pixel circuits, which has become an important research in the field of OLED panel design. This paper proposes 10 TFTs(thin film transistors)and 2 capacitor component driver circuits that has higher tolerance and better reliability regarding fluctuations such as display screen process, IC power signal noise, long‐term operation, etc.. [ABSTRACT FROM AUTHOR]

This paper offers the first demonstration of the design and layout of a fully integrated power converter in a monolithic Silicon Carbide (SiC) technology. A 400 V Buck Converter integrated with Gate-Drivers and Low-Voltage Control circuitry in a 25–600 V Mixed-Mode SiC CMOS technology has been presented in this paper. A new SiC technology has been developed for this design which has a feature size of 1 μm. This technology allows integration of High-Voltage Power FETs and Low-Voltage CMOS circuits on the same die with a common substrate. Both high-side and low-side Power FETs are N-type hence a bootstrap circuit is used, and the gate drivers use an isolated capacitive level shifter to translate the signals from the 25 V domain to the 400 V domain which is the input voltage of the Buck Converter. The load current is 1 A and the nominal output voltage is 100 V thereby meaning that the output power is 100 W. The switching frequency is up to 1 MHz, and the duty cycle can range from 10% to 90% signifying a wide range of operation of the converter. [ABSTRACT FROM AUTHOR]

Featured Application: The proposed solution for the high-power IGBT driver can be used as a reference for the design of similar intelligent gate drives, improving the reliability of power electronic converters in traction, industrial, and renewable energy applications. High-power IGBTs are used in power electronic converters in a variety of applications: traction drives, renewable power converters, mining equipment, oil and water pumping, and so on. To control a transistor, a special gate driver board is required. This board converts the logical control signal into the appropriate voltage values necessary to turn the resistor on and off. Gate drivers can perform the protection functions of IGBTs using hardware and algorithmic approaches. Application-specific integrated circuits are often used in driver solutions to implement control and protection. The development of an application-specific integrated circuit is a time-consuming and expensive procedure, which increases the cost of the driver. This paper describes the control and protection algorithms implemented in an intelligent IGBT driver based on a low-cost microcontroller. The use of the microcontroller makes the gate driver design more flexible and allows for the accurate tuning of the protection thresholds. The gate driver protects the IGBT from short-circuiting, overcurrent, and overvoltage, monitors the voltage supply, and controls the switch on and switch off processes in the transistor. The performance of the protection algorithms was tested experimentally using a specialized test bench. [ABSTRACT FROM AUTHOR]

This paper presents a hardware implementation for the reliable design of a full silicon carbide (SiC) inverter-fed motor drive system. SiC MOSFETs have been widely used in various applications due to their low switching losses, high voltage capabilities, and high-temperature operation capability. However, SiC MOSFETs are vulnerable to the overvoltage and overcurrent caused by the high switching frequencies and faults of parasitic inductance. The high speed of switching transitions causes high dv/dt, which leads to insulation failures of motor windings. In addition, the high di/dt, according to the parasitic inductance, can destroy the switching devices under short-circuit faults. A gate driver with desaturation protection is required to prevent short-circuit faults, and a passive filter should be installed to reduce the dv/dt to within prescribed values. This paper presents an optimized design process for a full SiC inverter-fed motor drive system with improved reliability. The effectiveness and validity of the process are verified through experimental results under various conditions. [ABSTRACT FROM AUTHOR]

A compact gate driver using p‐type low‐temperature polycrystalline silicon (LTPS) thin‐film transistors (TFTs) was proposed for Micro‐Light Emitting diodes (μLEDs) display using progressive emission analog pulse‐width modulation (A‐PWM) approach. The gate driver contains a simple waveform shaping module and outputs multiple sweep signals, including SW[n], EM[n], and S[n], by reusing the bootstrap node. Compared with conventional schemes, the proposed gate driver renders static power consumption reduction of the μLED display by 29.2%. [ABSTRACT FROM AUTHOR]

With high-frequency, low power dissipation and high-efficiency characteristics, Gallium nitride (GaN) power devices are of significant benefit in designing high-speed motor drives, as they improve performance and reduce weight. However, due to the cascode structure, coupling with the parasitics in gate driver and power circuits, power converters based on cascode GaN are prone to overshoot and oscillate on switching waveforms, which may lead to serious EMC problems, or even device breakdown. The complicated structure of cascode GaN device makes the gate driver design comparatively complex. An analytical model of the switching process considering gate driver parameters is proposed in this article. The influence of gate driver parameters on switching behavior is investigated from the perspective of switching speed, waveform overshoot, and power loss. Trade-offs among overshoot, switching speed, and power loss are discussed; guidelines to design gate driver parameters are given.

An adjustable gate driver is proposed based on the optimization of switching transient performances. The turn-on process is optimized through an adjustable charging current, while the turn-off process is optimized through an adjustable segmented drive current. The proposed gate drive circuit has the advantage of reducing switching loss, delay, and total switching time, while maintaining the switching stress and EMI noise level during both turn-on and turn-off transients. The proposed driver can be integrated into gate driver ICs, and the switching performance can be externally adjusted to match the power device for different applications. By combining the above techniques, an adjustable gate driver IC has been developed using the $0.25~\mu $ m BCD process. The simulated and experimental results validate the proposed technique. Compared to the conventional gate driver, the overshoot voltage has been reduced from 15.4% to 8.3%, and the overshoot current has decreased from 20.5% to 10.2% under a 10A load condition.

In this paper the design of a galvanically isolated data link for gate-driver applications in GaN technology is presented. The isolation channel exploits the near-field RF planar coupling between micro-antennas placed on two side-by-side co-packaged chips. Adopted package-scale isolation has several benefits i.e., the applicability to any integration technology and the capability to achieve both very high isolation rating and common-mode transient immunity by means of a proper distance between chips. The isolation channel adopts an RF carrier of 2 GHz that is modulated by a PWM signal. For the first time, a voltage-combining approach based on multiple antennas has been explored in a galvanically isolated data link. Specifically, the TX front-end consists of two capacitively coupled RF oscillators connected to two differential antennas designed for voltage combining. The RX front-end combines the transmitted RF signals by means of one differential antenna and extracts the PWM signal by means of a rectifier and an amplifier with a dynamic offset compensation. Emphasis is given to the design of micro-antennas, which is essential to minimize channel loss. The data link was tested by using a chip-on-board assembly to validate the proposed approach. The overall current consumption was lower than 4 mA for a PWM signal of 500 kHz and a duty cycle of 50%.

Fast switching within static converters is a key to high-efficiency operation and a source of electromagnetic disturbances that can harm the proper functioning of the converters themselves or the electronic equipment placed in their neighborhood. To characterize disturbances, engineers are mainly focused on the spectral content since the higher the switching speed, the more important the high-frequency components are. In this article, a figure of merit (FOM) independent of switching speed is proposed. It allows us to compare switching patterns produced by a gate driver to each other, using as a reference the mathematical optimum of a Gaussian pattern as well as other elementary forms for which the FOM is known. A complete implementation methodology is presented to properly use this FOM that considers an adapted sampling frequency and filtering of signals before processing in order to correctly obtain information for the optimal adjustment of a driver. [ABSTRACT FROM AUTHOR]

New semiconductor materials offer several advantages for modern power systems, including low switching and conduction losses, excellent thermal conduction of a die, and high operation temperature. Avionics is one of the main beneficiaries of the progress in power devices, as it enables more compact and lighter converters for future More Electrical Aircraft. However, these advancements also come with new challenges that must be addressed to avoid potentially dangerous situations and fully utilize the capabilities of fast SiC MOSFETs. One such challenge is the high drain voltage rate during the switching process, which leads to a significant injection of current into the gate circuit (crosstalk effect). This increased current injection increases the risk of shoot-through conduction and thermal runaway. Although preventive measures are well-known, they offer limited protection in the case of parallel MOSFET connections. Therefore, this paper considers crosstalk features for parallel MOSFET connections, such as parasitic inductance of gate driver trace and gate voltage distribution. A special model is proposed to predict the magnitude of induced gate voltage under different conditions considering the nonlinear behavior of the MOSFET reverse capacitance. A new clamp circuit with an individual low-inductance path for each parallel switch is also proposed to suppress the consequences of crosstalk. The modified circuit operates independently from the main gate driver circuit; therefore, it does not change the switching time and electromagnetic interference pattern of the inverter. The efficiency of the new gate driver is confirmed through simulation and experimental results.

Various methods have been discussed in the literature regarding enabling the over-current (OC) capability of silicon carbide (SiC) MOSFETs. SiC MOSFETs can operate at up to 250 °C without failure. One of their features is to permit transient operation at elevated temperatures. This is possible if the stress on the gate oxide and packaging can be kept to a level that can be handled. This paper, instead, investigates the potential of enabling the OC capability of SiC MOSFETs by modifying the gate-source voltage. Since the on-state resistance (RDS(on)) of SiC MOSFETs decreases with an increase in the gate voltage (VGS), the conduction losses can be decreased by increasing the VGS. Experiments and simulations have been performed to predict the RDS(on) with the increase in VGS. It is found that the simulation models provided by manufacturers can be used to predict RDS(on) accurately even outside the specifications, hence facilitating the precise estimation of conduction losses. It is also concluded that VGS can be increased during OCs in order to keep the conduction losses within the safety limits. A simple concept for implementing this function on a gate driver is also proposed with the additional functionality of increasing the VGS during OC by measuring the on-state voltage of the MOSFET.

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control.

Because of the benefits of lower on-state resistance, higher operating voltage, and higher switching frequency, SiC-MOSFET has gradually become an ideal choice for the development of power converters operating in high voltage, temperature, and power density. However, the greater dv/dt and di/dt during fast switching transients in the bridge circuit may produce substantial crosstalk problems on the complementary device due to parasitic characteristics of the device itself and its package, and with the lower turn-on threshold voltage and reverse voltage withstand capability, the crosstalk voltage will directly threaten its safe operation. This paper presents the association between the crosstalk voltage and the parameters in driving circuit and device according to the theoretical analysis of the crosstalk mechanism in a half-bridge circuit and based on the analysis, a gate driver circuit using auxiliary low-power Si-MOSFET are proposed to suppress the crosstalk spike without additional negative gate–source voltage or control signal and can be implemented with low cost and less complexity. The operation principle and parameter design of the key components are analyzed later. Finally, the simulation and experiment results show that proposed active clamped gate driver is effective at suppressing crosstalk.

High-power IGBTs are used in power electronic converters in a variety of applications: traction drives, renewable power converters, mining equipment, oil and water pumping, and so on. To control a transistor, a special gate driver board is required. This board converts the logical control signal into the appropriate voltage values necessary to turn the resistor on and off. Gate drivers can perform the protection functions of IGBTs using hardware and algorithmic approaches. Application-specific integrated circuits are often used in driver solutions to implement control and protection. The development of an application-specific integrated circuit is a time-consuming and expensive procedure, which increases the cost of the driver. This paper describes the control and protection algorithms implemented in an intelligent IGBT driver based on a low-cost microcontroller. The use of the microcontroller makes the gate driver design more flexible and allows for the accurate tuning of the protection thresholds. The gate driver protects the IGBT from short-circuiting, overcurrent, and overvoltage, monitors the voltage supply, and controls the switch on and switch off processes in the transistor. The performance of the protection algorithms was tested experimentally using a specialized test bench.

Digital isolators are implemented to protect low-voltage electronics and ensure human safety during high-voltage surge events. In this work, we present the design of an inductive-based digital isolation system that can sustain up to 1 kVrms breakdown voltage. The proposed system is designed using the pulse polarity modulation scheme and fabricated in a 0.35 μ m CMOS. Two identical dies are bounded within the IC package, with one die housing the transmitter (Tx) and the isolation transformer, while the other die contains the receiver (Rx). Two different customized designs between three metal layers are implemented to form the isolation element. The transformer's secondary coil is constructed in metal-1, while the primary coil is formed in metal-2 and metal-3 for comparing the system functionality, isolation capability, and propagation delay. The functionality has been verified by measurements for an operating frequency of 300 MHz with a 2.6 ns propagation delay and an energy consumption of 8.15 × 103 pJ/bit at 1 Mbps. The chip was tested under extreme temperatures and achieved a maximum measured common mode transient immunity (CMTI) of 500 V/ μ s. Jitter has been examined to ensure fast transmission at a bit error rate (BER) of 10−15 with a total jitter (TJ) of 188.18 ps. [ABSTRACT FROM AUTHOR]

Voltage source inverters play a crucial role in connecting numerous renewable energy sources to the grid. The hardware performances and efficiency of these inverters relies on a compatible and efficient gate driver, the bootstrap circuit is a reliable technique for controlling the gates of inverter switches. Therefore, this article addresses the issue of designing and implementing a three-phase two-level voltage inverter with a gate driver based on a bootstrap circuit. However, inaccuracies in electronic components selection for the bootstrap circuit can potentially lead to a lack of compatibility between the inverter and the gate driver. Consequently, this Incompatibility may engender complications and impede the proper functioning of the inverter. This paper presents the necessary steps for implementing the inverter and the bootstrap gate driver, with a specific focus on the bootstrap circuit. The experimental results obtained from the implemented inverter validate the feasibility and functionality of the circuits. The paper provides detailed explanations of each circuit component through schematics and discusses the testing and validation processes of the implemented inverter and gate diver. [ABSTRACT FROM AUTHOR]

This article presents the concept of switching and conduction loss reduction in a T-NPC inverter based on IGBT transistors. The method of limiting switching losses involves the connection of an LC circuit designed to cause transistors in vertical branches to shut down under zero voltage conditions. In order to reduce conduction losses, it was proposed to use two reverse blocking transistors connected anti-parallel in the horizontal branch of the inverter. To ensure safe operation of the transistors, a gate driver proposal for controlling the IGBT reverse blocking transistor is presented. The solution is characterized by a changed part of the driver, responsible for short-circuit protection. It eliminates excessive, destructive currents that can potentially flow through the driver circuit under the influence of the power supply voltage of the power circuit connected backwards to the controlled transistor. Examples of applications and benefits of the proposed solution are presented and verified with laboratory tests. [ABSTRACT FROM AUTHOR]

We propose a novel gate driver generating positive pulse for oxide switching TFTs in AMOLED pixel circuits using low‐temperature polycrystalline silicon and oxide (LTPO) thin‐film transistors (TFTs). The proposed gate driver circuit has only five TFTs without capacitor. The proposed circuits can operate perfectly when all oxide TFTs in the circuits have threshold voltage (VTH) of ‐3.5V, depletion mode. The circuit can be easily designed for narrow bezel due to simple structures. The one stage of the circuit was designed with the size of 50 μm × 100 μm. The fabricated circuit works well with the depletion mode oxide TFTs with VTH of ‐3.5V. The circuit operated at the pulse width of 1 μs, corresponding to operating speed of 500 kHz. The proposed gate driver can be applicable for narrow bezel AMOLED display. [ABSTRACT FROM AUTHOR]

This paper presents a three-level gate driver for GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) for high false turn-on tolerance and low reverse conduction loss during both dead time at turn-on and turn-off. The proposed gate driver reduces the reverse conduction loss by clamping between the gate and source terminals only during dead time. It has a capacitor which works as a negative voltage source and prevents from the false turn-on phenomenon. It operates only with a single voltage source and a PWM (Pulse Width Modulation) output signal. The proposed gate driver is implemented on a 48V-to-12 V synchronous rectifier buck (SR-buck) converter and compared with other countermeasure methods for the false turn-on phenomenon. At the condition of 1 MHz, 30 ns dead time, and 120 W output power, the efficiencies of the proposed and conventional operations are 95.1% and 92.8% respectively. The margin between the threshold voltage and the peak of oscillated voltage of the proposed method becomes 1.3 times larger than that of the conventional method on average.

Noise immunity is a critical index of high-voltage half-bridge gate driver integrated circuits (IC). Various noise cancelation technologies have been proposed to improve dv/dt noise immunity with sacrifices in terms of area and propagation delay time. Besides, when it is applied to an inductive load, the half-bridge driver is vulnerable to negative surges at the VS terminal, which is the offset ground of the high-side channel. A 300 V half-bridge gate driver IC with noise rejection module is designed in this paper. The noise immunity can be improved to 87.5 V/ns. The VS negative swing region can be extended to − 5.1 V. In addition, the proposed driver IC can work normally at a working frequency of 500 kHz and the delay matching time between the high-side and the low-side is less than 4 ns. The propagation delay time of the high-side channel is measured at 71.6 ns. Furthermore, gamma ray irradiation experimental results show that the proposed structure presents a good radiation tolerance of 100 krad (Si). The presented half-bridge gate driver IC is fabricated with the silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, which occupied an area of 1.86 mm2. [ABSTRACT FROM AUTHOR]

This article presents a gate driver circuit with all-magnetic isolation for driving silicon carbide (SiC) power devices in a three-level T-type bridge-leg. Gate driver circuitry for SiC devices has to be tolerant of rapid common-mode voltage changes. With respect to the resultant potentially problematic common-mode current paths, an arrangement of transformers is proposed for supplying the power devices with drive signals and power for their local floating gate driver circuits. The high-frequency carrier phase-switching technique is used to reduce the number of transformers. Signal timing and other implementation issues are addressed when using this arrangement with the T-type converter. The circuit is demonstrated in a 540 V bridge-leg constructed around 650 V and 1200 V cascode-connected normally-on SiC junction field effect transistors (JFETs). [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN) devices are generally more prone to severe switching oscillations than Si mosfets due to their fast switching speeds. Different from Si and SiC mosfets, GaN devices typically have a lower maximum gate voltage rating. Taking the Efficient Power Conversion Corporation series as an example, the gate drive voltage is usually 5 V, but the maximum voltage rating is 6 V. Therefore, GaN devices are more susceptible to damage from gate-source voltage oscillation. In this letter, a gate drive circuit with a clamping function is proposed to suppress gate-source voltage oscillation. The adopted method can not only clamp the gate voltage of the GaN device near the drive voltage to protect the device, but also does not affect the switching speed of the device. The proposed method mainly uses some passive components that make the circuit design simpler compared with other active gate driver methods. Finally, the effectiveness of the proposed method is verified by experiments. [ABSTRACT FROM AUTHOR]

• A dual-bootstrapping TFT integrated gate driver circuit. • Amorphous indium-gallium-zinc-oxide (a-IGZO) TFT circuit integration technology. • A 39% reduction in falling time. • The over-drive voltage of the driving TFT is increased both at the rising and falling edges of the output waveforms. To promote the integration of thin-film transistor (TFT) gate driver circuit technology into high-resolution large-size display application with narrow bezel, achieving high speed is a critical challenge. This paper proposed a dual-bootstrapping TFT integrated gate driver circuit for large-size display. The over-drive voltage of the driving TFT was increased both at the rising and falling edges of the output waveforms. To validate the circuit feasibility, the proposed circuit was fabricated using amorphous indium-gallium-zinc-oxide (a-IGZO) TFT technology and measured in terms of transient response with cascaded stages and reliability tests over long operating time. Compared to conventional approaches, the proposed gate driver demonstrates a 39 % reduction in the falling time as well as compact layout. Therefore, the proposed gate driver schematic is well-suited for large-size display applications that involves heavy resistance–capacitance (RC) loadings and require high resolution above 8 K. [ABSTRACT FROM AUTHOR]

This letter presents a partial-bootstrap gate driver circuit for switching loss reduction and crosstalk mitigation. The proposed circuit is simple and no additional power supply or control is needed. The circuit structure and operating principles of the proposed gate driver are introduced. Three different operating modes of the proposed gate driver are presented. Finally, the experimental results are presented to validate the proposed gate driver. It is found that the proposed gate driver can greatly accelerate the switching process and reduce switching loss. The proposed gate driver can also generate a gradually decaying negative voltage during the turn-off process to suppress crosstalk. [ABSTRACT FROM AUTHOR]

1500-V photovoltaic (PV) configuration is the standard design in the solar PV industry. Extending the maximum dc voltage from 1000 to 1500 V can reduce the installation cost of the entire power plant. However, it may affect the reliability of the corresponding 1500-V PV inverters, due to the increased loading stresses, i.e., voltage stress and thermal loading of power devices. In this context, this article proposes a solution to the reliability enhancement of silicon carbide-mosfet-based 1500-V PV inverters with variable gate resistance. This solution offers a possibility to adaptively adjust the switching speed to make a compromise between the switching power loss and voltage overshoot during commutation, thus enhancing the reliability. The evaluation results based on the mission profile of a 125-kW 1500-V PV system installed in Denmark indicate that the PV inverter with the proposed design, i.e., variable gate resistance, can improve reliability performance compared to the fixed gate resistance solution while ensuring a safer operating voltage margin. [ABSTRACT FROM AUTHOR]

DC circuit breaker is the key equipment to deal with the interruption of short-circuit current. Compared with the mechanical switch, the solid circuit breaker and the hybrid circuit breaker using the semiconductor device to interrupt the short-circuit current exhibit superiorities in response duration and arc-less characteristics. Massive power devices controlled by corresponding gate drivers which make the semiconductors-based dc circuit breaker bulky and costly are required to withstand the high dc-bus voltage. In this article, the master−slave concept based modular circuit breaker is proposed to simplify the gate driver topology. Only one single gate driver is required to control highly compact modular submodules consisting of power devices, passive components, and diodes. Moreover, the proposed topology can be easily implemented with high flexibility and low cost. Specifically, the gate control function and voltage equalization for series-connected devices can be realized reliably. The master−slave concept and operation principle of the proposed topology are elaborated and the effectiveness has been demonstrated by both simulation and experimental test. [ABSTRACT FROM AUTHOR]

We report a 38 $\mu \text{m}$ -pitch gate driver with three outputs using low-temperature poly-Si oxide (LTPO) thin-film transistors (TFTs) for ultra-high definition (UHD) display. A single stage of the proposed gate driver circuit consists of ten TFTs, six p-type low-temperature poly-Si (LTPS) and four n-type amorphous InGaZnO (a-IGZO) TFTs for three outputs. Three clock (CLK) signals are used for three outputs in one stage. The fabricated gate driver circuit, using the depletion mode a-IGZO TFTs with threshold voltage ($\text{V}_{{{\mathrm {TH}}}}$) of −3.5 V, successfully operates with a pulse width of $1~\mu \text{s}$. This can be used for 8k4k resolution display operated at refresh rate of 240 Hz. The power consumption can be as low as 9.4 mW at 4k2k ($3840\times2160$) resolution operated at 120 Hz. The proposed gate driver therefore can be utilized for UHD display with LTPO TFT backplane. [ABSTRACT FROM AUTHOR]