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A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push–pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs.

A continuous-time bandpass ΔΣ modulator (CTBPDSM) is a good solution for software-defined-radio (SDR) since it allows much flexibility in the digital backend and also decreases the complexity of the receiver chain by combining several analog blocks into a single ADC [1]. However, conventional CTBPDSMs suffer from large power consumption and occupy large area. CTBPDSMs based on LC tanks are large, while biquad-based resonators are also large and suffer from high power consumption because two amplifiers are usually required in each resonator. The fact that there are typically twice as many feedback paths compared to a lowpass ΔΣ modulator with the same bandwidth and performance also increases power consumption, area and complexity. This paper presents a power-efficient resonator with a single amplifier and also introduces a simplified architecture utilizing return-to-zero (RZ) and half-clock-delayed return-to-zero (HZ) pulses to solve the power and complexity problems.

A low-power 14-b 100-MS/s analog-to-digital converter (ADC) is described. The prototype ADC achieves low-power consumption and small die area by sharing an opamp between two successive pipeline stages. Further reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp and capacitor sharing technique. The ADC, implemented in a 0.18-mum dual-gate-oxide (DGO) CMOS technology, achieves 72.4-dB signal-to-noise and distortion ratio, 88.5-dB spurious free dynamic range, and 11.7 effective number of bits at full sampling rate with a 46-MHz input while consuming 230-mW from a 3-V supply.

A bandpass modulator with two time-interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40 MHz IF provide a signal band of 1 MHz with 72 DR and 65.1 dB peak SNR. The circuit, integrated in a 0.18 CMOS technology, uses a 60 MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an IMD signal of 68 . The power consumption is 16 mW with 1.8 V supply.