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A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC
- Source :
- IEEE Journal of Solid-State Circuits. 43:2613-2619
- Publication Year :
- 2008
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2008.
-
Abstract
- A low-power 14-b 100-MS/s analog-to-digital converter (ADC) is described. The prototype ADC achieves low-power consumption and small die area by sharing an opamp between two successive pipeline stages. Further reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp and capacitor sharing technique. The ADC, implemented in a 0.18-mum dual-gate-oxide (DGO) CMOS technology, achieves 72.4-dB signal-to-noise and distortion ratio, 88.5-dB spurious free dynamic range, and 11.7 effective number of bits at full sampling rate with a 46-MHz input while consuming 230-mW from a 3-V supply.
- Subjects :
- Engineering
Spurious-free dynamic range
business.industry
Amplifier
Pipeline (computing)
law.invention
Reduction (complexity)
Effective number of bits
CMOS
law
Low-power electronics
Hardware_INTEGRATEDCIRCUITS
Operational amplifier
Electronic engineering
Hardware_ARITHMETICANDLOGICSTRUCTURES
Electrical and Electronic Engineering
business
Subjects
Details
- ISSN :
- 00189200
- Volume :
- 43
- Database :
- OpenAIRE
- Journal :
- IEEE Journal of Solid-State Circuits
- Accession number :
- edsair.doi...........483638dcd71b9c5e454557fa875f6c09