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We have designed new process architecture for high-density magneto-resistive random access memory (MRAM). One of the major issues in fabricating high-density MRAM is how to prevent the electrical short through the tunnel barrier without any kind of degradation of the characteristics of small magnetic tunnel junction (MTJ) devices. We have developed a novel MTJ patterning technique that involves removing the residual free layer by wet-chemical treatments after partial RIE process. Additional degradation of MTJ devices in post-patterning should be minimized.

Programming with larger current than optimized one is often preferable to ensure a good resistance distribution of high-resistive reset state in high-density phase-change random access memories because it is very effective to increase the resistance of cells to a target value. In this paper, we firstly report that this larger current writing may conversely degrade the reset distribution by reducing the resistance of normal cells via the partial crystallization of amorphous Ge2Sb2Te5 and this degradation can be suppressed by designing a novel cell structure with a heat dissipating layer.

Fully functional 512Mb PRAM with 0.047mum2 (5.8F2) cell size was successfully fabricated using 90nm diode technology in which the authors developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge2Sb2Te5. The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85degC

Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge2Sb2Te5 (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond

Advanced bottom electrode contact (BEC) scheme was successfully developed for fabricating reliable high density 64 Mb PRAM by using ring type contact scheme. This advanced ring type BEC scheme was prepared by depositing very thin TiN films inside a contact hole, and then core dielectrics was uniformly filled into the TiN-deposited contact hole. Using this novel contact scheme, it was possible to reduce a reset current with low set resistance, and also maintain a uniform cell distribution. Thus, it is clearly demonstrated that the ring type BEC technology can exhibit strong feasibility of high density 256 Mb PRAM and beyond.

Novel small contact fabrication technologies were proposed to realize reliable high density 256Mb PRAM(phase change memory) product. Introducing the 2-step CMP (chemical mechanical polishing) process and the ring-shaped contact structure, the contact area distribution was greatly improved even at the smallest contact diameter of 50nm node. The validity of this approach was directly confirmed by the evaluation of the functionality for the fabricated 256Mbit PRAM based on 0.10/spl mu/m CMOS technology.

A 64 Mb phase change random access memory, based on 0.18 /spl mu/m technology is developed. We proposed several key factors such as BEC and GST cell size, contributing to stabilization of writing current for reversible cell transition. By reducing writing current to 1.1 mA through such optimization, we have developed a 64 Mb PRAM. With memory functions and reliability tests, the feasibility for developing high-density 64 Mb PRAM is presented.

A novel 8F/sup 2/ cell structure for high density magnetic random access memory (MRAM) and its operating characteristics are proposed. In this new scheme, we formed bottom electrode contact (BEC) through twin metal lines (MLs) and a magnetic tunnel junction (MTJ) was located just on the BEC for the reduction of cell size. From the results of simulation and experiment, we have confirmed that the generated magnetic field in the new scheme is more uniform than that in the conventional scheme with a negligible reduction of writing field strength. We adopted a self-aligned BEC process to prevent electrical shorting between ML and BEC. To avoid electrical shorting and improve the magnetic properties of MTJs, a chemical mechanical polishing (CMP) process was adopted before MTJ deposition. As a result, we confirmed the feasibility of high-density 1T1MTJ MRAM, composed of 8F/sup 2/ cells with optimal MTJ characteristics.

The DRAM process technology has been on the leading edge of semiconductor technology, and the density of DRAM has been quadrupled every three years. 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) was successfully manufactured and much attention is now given to the process technology for 4 Gb DRAM based on 0.15 /spl mu/m technology node or smaller than 0.15 /spl mu/m technology node. 0.15 /spl mu/m technology node is considered to be transition node between 0.18 /spl mu/m which KrF lithography is used on 200 mm wafers and 0.13 /spl mu/m node in which ArF lithography will be used on 300 mm wafers. In this paper, key process and integration technologies for 0.15 /spl mu/m DRAM technology node are developed in order to satisfy both 0.18 /spl mu/m technology node and 0.13 /spl mu/m node. The process and integration technologies employed in 0.15 /spl mu/m technology node are verified with an experimental 16 Mb DRAM.

We have demonstrated fully integrated 64 kb magnetoresistive random access memories (MRAM) with 0.24 μm CMOS technology. With the proper control of magnetic tunnel junction (MTJ) and subsequent process, we obtained tunneling magnetoresistive characteristics free of electrical shorting and we could minimize the degradation of MTJ. We confirmed MRAM operation without fail bit increase for write pulse width down to 6 ns. We confirmed the endurance of 64 kb MRAM up to 108 read/write cycles.