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This paper presents a sub-electron temporal readout noise, 8.3 Mpixel and 1.1- $\mu \text{m}$ pixel pitch 3-D-stacked CMOS image sensor (CIS). A conditional correlated multiple sampling (CMS) technique is introduced to selectively reduce the dark pixel noise by using a full-range ramp and a small-range ramp. In this way, a sub-electron temporal readout noise CIS is achieved without degrading the frame rate dramatically, compared to the conventional CMS method. A column-parallel single slope ADC with dark pixel detection function is proposed as well. A dynamic-dark-signal-region detection technique is used to mitigate differential nonlinearity (DNL) errors due to ramp slope mismatch. The implemented prototype in 45-nm CIS/65-nm CMOS occupies an area of 35.89 mm2. This paper achieves a 0.66erms− with 5-time sampling at a frame rate of 7.2 frames/s, which corresponds to a sample-rate frequency of 36.1 kHz for the column ADC. The DNL (11 b) is improved from +0.98 LSB/−0.94 LSB to +0.29 LSB/−0.39 LSB by using dynamic dark-signal region technique. The figure of merit of this paper is 2.02 nVrms/Hz.

A new method for on-chip random telegraph noise (RTN) characteristic time constant extraction using the double sampling circuit in an 8.3 Mpixel CMOS image sensor is described. The dependence of the measured RTN on the time difference between the double sampling and the key equation used for time constant extraction are derived from the continuous time RTN model and the discrete event RTN model. Both approaches lead to the same result and describe the data reasonably well. From the detailed study of the noisiest 1000 pixels, we find that about 75% to 85% of them show the signature of a single-trap RTN behavior with three distinct signal levels, and about 96% of the characteristic time constants fall between 1 ${\mathrm{ \mu }}\text{s}$ and 500 ${\mathrm{ \mu }}\text{s}$ with the median around 10 ${\mathrm{ \mu }}\text{s}$ at room temperature.

By using periodical electromagnetic bandgap (EBG) structure, a wideband band-stop filter (BSF) with ESD protection is first realized in 16-nm FinFET CMOS technology for GHz-order noise suppression. The proposed EBG unit cell consists of an on-chip inductor in series with MOS capacitors and gated ESD diodes. The gated ESD diodes are not only used as ESD protection devices, but also co-designed with MOS capacitors and an inductor to form LC resonator for the BSF. The measurement results demonstrate TLP currents of 1.75 A and 1.35 A for the PDS and NDS modes, respectively, corresponding to a HBM ESD level over 2 kV. With the consideration of metal density rule for power/ground mesh, the on-chip EBG array presents a stopband of 15.5 GHz, from 4.5 to 20 GHz, with an isolation level of 30 dB.

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of −106 dBc/Hz (FoM of −239.2 dB) and RMS jitter of 0.86ps while dissipating only 1.6mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.

We propose a new approach to an on-chip clock distribution scheme. It is based on distributed multi-GHz LC-tank oscillators generating local clocks. The oscillators are mutually coupled to align their frequencies and are further subharmonically injection-locked to a much lower frequency reference to align their phases. The final phase calibration is via adjusting their self-resonant frequencies. We demonstrate the scheme with two 4GHz digitally controlled oscillators (DCO) separated by 650um on a 16nm CMOS die, mutually coupled via a differential transmission line and injection-locked to a 125MHz reference. The proposed architecture achieves a sub-ps calibrated skew with 87fs rms jitter while consuming 4.3mW, resulting in −258dB clock FOM (jitter2 × power).

We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F2 digital power amplifier (PA), featuring high efficiency. Low 1/ f DCO noise allows the ADPLL to shut down after acquiring lock. The receiver operates in discrete time at high sampling rate (10 Gsamples/s) with intermediate frequency placed beyond 1/ f noise corner of MOS devices. New multistage multirate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise, and low power consumption. An integrated on-chip matching network serves to both PA and low-noise transconductance amplifier, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The TRX consumes 2.75 mW on the RX side and 3.7 mW on the TX side when delivering 0 dBm in BLE.

The pinned photodiode capacitance extraction method proposed by Goiffon et al. is discussed, and two additional new methods are presented and analyzed; one based on the full well dependence on photon flux and the other based on the full well dependence on transfer-gate off-voltage.

This paper presents two 60-GHz low-noise amplifiers (LNAs) with different electrostatic (ESD) protection schemes, including the diode-based and LC-based configurations. By codesigning ESD network and input matching, both LNAs are optimized for minimum noise figure (NF) while maintaining a similar gain. Compared with the conventional double-diode approach, the proposed LC-based design uses a high current capability spiral inductor and a high breakdown voltage metal-oxide-metal capacitor as effective bidirectional ESD protection, showing much improved ESD protection level and NF under reduced power consumption. The test results demonstrate an over 8-kV human-body-model ESD level and an over 13-A very fast transmission line pulse current level for charge-device-model ESD protection. The measured NF and power gain are 5.3 dB and 17.5 dB, respectively, at 58 GHz, under a power consumption of only 18 mW. To the best of our knowledge, the LC-based ESD-protected LNA demonstrates a highest ESD protection level with a lowest NF, compared with prior arts operating at similar frequencies.

We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s) discrete-time (DT) architecture with intermediate frequency (IF) placed beyond the 1/f noise corner of MOS devices. New multistage multi-rate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise and low power consumption. A transmitter (TX) employs an all-digital PLL (ADPLL) with switched-current-source digitally controlled oscillator (DCO) and switching PA. An integrated on-chip matching network serves both PA and LNTA, thus allowing a 1-pin direct antenna connection with no external antenna filters. The transceiver consumes 2.75mW in RX and 3.6mW in TX when delivering 0 dBm in Bluetooth LE.

Stacked-gate is one of the most popular solutions used in mismatch-sensitive circuits in FinFET technology. A Bandgap circuit using stacked-gate formed by 150 short-channel devices to achieve high accuracy is demonstrated. Adding uniform surrounding patterns to the target MOS array, the device mismatch caused by DGE (density gradient effect) can be cancelled. In low-power RF LNA and VCO, dc power reductions are achieved. The near-threshold-voltage (NTV) design technique is adopted for further 50% RF power reduction.

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode. European Research Council

This Forum is intended to provide an in-depth overview of noise modeling and simulation, and of analog, mixed-signal, and system-level solutions for low-noise sensing. State-of-the-art techniques to tackle noise in image sensors, mechanical sensors, temperature sensors, magnetic sensors and bio-sensors will be critically analyzed. The forum will explicitly address the trade-off between noise and energy consumption in such sensors, thus providing the audience with valuable insight into the design of sensor interfaces for the Internet of Everything

The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past few years. Among those cutting-edge interface technologies, multi-band (multi-tone) signaling has shown great potential because of its high data-rate capability along with its low energy consumption [3]–[5]. With spectrally divided signaling, the multi-band transceiver can be designed to avoid spectral notches with extended communication bandwidth of multi-drop buses [4]. Also, its unique self-equalized double-sideband signaling renders the multi-band transceiver immune to inter-symbol interference caused by channel attenuation without additional equalization circuitry [5]. To further improve the capability and validate the scalability of multi-band signaling, we have realized a tri-band transceiver with four parallel lanes and achieved a total data rate of 40Gb/s, with total power consumption of 38mW in 28nm CMOS technology.

This paper proposes a 55 nm CMOS 12-bit current-steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the video DAC can meet several different specifications in the power optimized (PO) mode. Furthermore, for DAC, the proposed 3S method, including finger separating, splitting and shifting, achieves good differential nonlinearity (DNL) performance to 0.78/0.4 least significant bit (LSB) and integral nonlinearity (INL) 1.3/1.0 LSB (with/without SIDO converter) without additional calibration. It also suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power efficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing and 1 MHz input. The proposed intrinsic 12-bit DAC and SIDO converter achieve high definition video DAC performance with the benefit of area and energy efficiency.

This paper presents two K-band low-noise amplifiers (LNAs) in 65-nm CMOS using the proposed RF junction varactors as the ESD protection devices. The junction varactors are customized for the RF ESD applications with accurate equivalent circuit models. The experimental results demonstrate excellent second breakdown currents (It2) and high ratios of the ESD level to parasitic capacitances (VESD/CESD) . Using the dual-diode topology, the first LNA demonstrates an over 2-kV Human-Body-Model (HBM) ESD protection level with a noise figure (NF) of 2.8 dB and a peak gain of 14.3 dB at around 24 GHz under a power consumption of only 7 mW. By incorporating an RF junction varactor as the extra gate-source capacitance at the input stage as a part of the ESD network, the second LNA presents an enhanced failure current level up to 2.6 A (corresponding to an HBM ESD level of 3.9 kV), and a Charge-Device-Model (CDM) ESD level up to 10.7 A, characterized by the Very Fast Transmission Line Pulse (VFTLP) tests. The second LNA shows a NF of 3.2 dB and a power gain of 13.7 dB, also under 7 mW.

ESSCIRC 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 14 - 18 September 2015

A conditional correlated multiple sampling (CCMS) technique for low noise CMOS image sensor (CIS) is proposed to reduce noise and address low frame rate issue caused by the conventional correlated multiple sampling (CMS) technique. An 8Mpixel 3D-stacked CIS with 1.1um pixel pitch is designed and verified. Measurement results show this technique can achieve 0.66e− rms at 36.1 kHz A/D sampling rate per pixel with analog gain at 16 and 5-times multiple sampling. The resulting DNL is within −0.49/+0.45LSB.

This paper investigates the microwave lowpass filters in integrated fan-out wafer-level packaging (InFO-WLP) technology. The Chebyshev prototype is adopted to achieve sharp cutoff at the edge of passband. A lumped-LC structure and three different distributed structures, including λ/8 stubs, stepped-impedance, and periodic tapered electromagnetic bandgap (EBG), are employed to find an appropriate microwave LPF realized in InFO-WLP technology. The simulation results exhibit the proposed LPF using lumped-LC structure can achieve the smallest size with the accepted ripple in passband and good suppression in stopband at the cutoff frequency of ∼ 10 GHz. To the best of authors' knowledge, this is the first to study microwave filters in InFO-WLP technology.

By co-design methodology, an integrated 2.4 GHz band-pass filter using grounded spiral inductors symmetrically at input/output ports for ESD protection is realized in integrated passive device (IPD) technology. With the novel input/output admittance-inverter (J-inverter) and the weakly coupled transformer, the transmission zeros can be introduced to increase the stop band attenuation. Also, the shunt inductor with enough vias in metal crossover is performed to enhance ESD current handling. It provides an effective bi-directional ESD protection to the ground. The experimental results demonstrate an over 8-kV HBM ESD protection can be achieved. The ESD-protected BPF presents an insertion loss of 1.6 dB at 2.4 GHz with only ∼ 0.4 dB degradation compared to BPF without ESD protection.

The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL's high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.