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A gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) shows great promise for low-power (sub-0.5 V) applications. A detailed investigation, with the help of a numerical device simulator, on the effects of variation in different structural parameters of a GoGeS TFET on its electrical performance is reported in this paper. Structural parameters such as κ -value of the gate dielectric, length and κ -value of the spacer, and doping concentrations of both the substrate and source are considered. A low-κ symmetric spacer and a high- κ gate dielectric are found to yield better device performance. The substrate doping influences only the p–i–n leakage floor. The source doping is found to significantly affect performance parameters such as OFF-state current, ON-state current and subthreshold swing, in addition to a threshold voltage shift. Results of the investigation on the gate length scaling of such devices are also reported in this paper. [ABSTRACT FROM AUTHOR]

A tunnel field-effect transistor (FET) (TFET), in which the dominant carrier tunneling occurs in a direction that is in line with the gate electric field, shows great promise for sub-0.6-V operation. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer–drain overlap on the device characteristics of such silicon TFET is reported in this paper. It is demonstrated that a supersteep subthreshold swing and a significantly reduced off-state current IOFF can be achieved by appropriate designing of the spacer–drain overlap. An investigation of the influence of the drain potential on the device characteristics reveals that the absence of a tunnel-resistance limited region results in long-channel metal–oxide–semiconductor FET-like output characteristics for such a structure. Short-channel effects, such as drain-induced barrier lowering, are also greatly suppressed in it. Results of the investigation on the scaling properties of such devices are also reported. [ABSTRACT FROM AUTHOR]

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities κ. It is observed that there is a decrease in the parasitic outer fringe capacitance Cof in addition to an increase in the internal fringe capacitance Cif with high-κ dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-κ integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum κ for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering. [ABSTRACT FROM AUTHOR]