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75 results on '"Freescale semiconductor"'

1. A semiconductor switch arrangement

Author: FREESCALE SEMICONDUCTOR INC A
Abstract: A semiconductor switch arrangement (300) comprising a bipolar transistor (302) and a semiconductor power switch (301) having an input node (306), an output node (304) and a control node (305) for allowing a current path to be formed between the input node (306) and the output node (307), wherein the bipolar transistor (302) is coupled between the input node (306) and the control node (305) to allow a current to flow from the input node (306) to the control node (305) upon a predetermined voltage being exceeded at the input node (306) to allow the control node (305) to cause a current to flow from the input node (306) to the output node (307).

2. Interface-based tuning of Rashba spin-orbit interaction in asymmetric oxide heterostructures with 3d electrons

Author: Shijie Wang, Xiaojiang Yu, Weinan Lin, Tom Wu, H. Rotella, Aurelien Manchon, Wilfrid Prellier, Stephen J. Pennycook, Zhicheng Zhong, Bangmin Zhang, Changjian Li, Yangyang Li, Jingsheng Chen, Lei Li, Fatih Dogan, Wen Siang Lew, Laboratoire de cristallographie et sciences des matériaux (CRISMAT), École Nationale Supérieure d'Ingénieurs de Caen (ENSICAEN), Normandie Université (NU)-Normandie Université (NU)-Centre National de la Recherche Scientifique (CNRS)-Université de Caen Normandie (UNICAEN), Normandie Université (NU)-Institut de Chimie du CNRS (INC), Nanayang Technological University, Freescale Semiconductor, Inc., Austin, Freescale Semiconductor, Inc., Austin TX, Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Ingénieurs de Caen (ENSICAEN), Normandie Université (NU)-Normandie Université (NU)-Université de Caen Normandie (UNICAEN), Normandie Université (NU), Southeast univ., King Abdullah University of Science and Technology (KAUST), School of Physical and Mathematical Sciences, National University of Singapore (NUS), Nanyang Technological University [Singapour], Chinese Academy of Sciences [Beijing] (CAS), American University of The Middle East [Eqaila], Université de Caen Normandie (UNICAEN), Normandie Université (NU)-Normandie Université (NU)-École Nationale Supérieure d'Ingénieurs de Caen (ENSICAEN), Normandie Université (NU)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche sur les Matériaux Avancés (IRMA), Normandie Université (NU)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université de Rouen Normandie (UNIROUEN), Normandie Université (NU)-Institut national des sciences appliquées Rouen Normandie (INSA Rouen Normandie), Institut National des Sciences Appliquées (INSA)-Normandie Université (NU)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université de Rouen Normandie (UNIROUEN), Institut National des Sciences Appliquées (INSA)-Normandie Université (NU)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), Agency for science, technology and research [Singapore] (A*STAR), Chinese Academy of Social Sciences [Beijing] (CASS), and University of New South Wales [Sydney] (UNSW)
Subjects: 0301 basic medicine, Electronic Properties and Materials, Electronic properties and materials, Science, Point reflection, General Physics and Astronomy, 02 engineering and technology, Electron, Article, General Biochemistry, Genetics and Molecular Biology, 03 medical and health sciences, Condensed Matter::Materials Science, Atomic orbital, Physics [Science], [CHIM]Chemical Sciences, [PHYS.COND]Physics [physics]/Condensed Matter [cond-mat], lcsh:Science, Quantum, ComputingMilieux_MISCELLANEOUS, Physics, [PHYS]Physics [physics], Multidisciplinary, Spintronics, Condensed matter physics, Heterojunction, General Chemistry, Spin–orbit interaction, [CHIM.MATE]Chemical Sciences/Material chemistry, 021001 nanoscience & nanotechnology, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, 030104 developmental biology, lcsh:Q, [PHYS.COND.CM-SCE]Physics [physics]/Condensed Matter [cond-mat]/Strongly Correlated Electrons [cond-mat.str-el], 0210 nano-technology, Rashba effect
Abstract: The Rashba effect plays important roles in emerging quantum materials physics and potential spintronic applications, entailing both the spin orbit interaction (SOI) and broken inversion symmetry. In this work, we devise asymmetric oxide heterostructures of LaAlO3//SrTiO3/LaAlO3 (LAO//STO/LAO) to study the Rashba effect in STO with an initial centrosymmetric structure, and broken inversion symmetry is created by the inequivalent bottom and top interfaces due to their opposite polar discontinuities. Furthermore, we report the observation of a transition from the cubic Rashba effect to the coexistence of linear and cubic Rashba effects in the oxide heterostructures, which is controlled by the filling of Ti orbitals. Such asymmetric oxide heterostructures with initially centrosymmetric materials provide a general strategy for tuning the Rashba SOI in artificial quantum materials., The two-dimensional electron gases that form at LaAlO3/SrTiO3 heterostructure interfaces feature strong spin-orbit interactions, leading to proposed spintronic applications. Lin et al. show that the design of asymmetric heterostructures enables the Rashba spin-orbit interaction to be tuned between two regimes.
Published: 2019
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3. Fatigue crack growth versus plastic CTOD in the 304L stainless steel

Author: C. Gardin, Pedro Prates, M.S.C. Ferreira, Fernando Antunes, C. Sarrazin-Baudoux, Ricardo Branco, Freescale Semiconductor (FREESCALE SEMICONDUCTOR), Freescale semiconductor, Institut Pprime (PPRIME), ENSMA-Centre National de la Recherche Scientifique (CNRS)-Université de Poitiers, ENDOmmagement et durabilité ENDO (ENDO), Département Physique et Mécanique des Matériaux (Département Physique et Mécanique des Matériaux), ENSMA-Centre National de la Recherche Scientifique (CNRS)-Université de Poitiers-ENSMA-Centre National de la Recherche Scientifique (CNRS)-Université de Poitiers-Institut Pprime (PPRIME), and ENSMA-Centre National de la Recherche Scientifique (CNRS)-Université de Poitiers-ENSMA-Centre National de la Recherche Scientifique (CNRS)-Université de Poitiers
Subjects: Materials science, 304L stainless steel, [PHYS.MPHY]Physics [physics]/Mathematical Physics [math-ph], 02 engineering and technology, Fatigue crack growth, [SPI.AUTO]Engineering Sciences [physics]/Automatic, Stress (mechanics), Crack closure, 0203 mechanical engineering, [PHYS.QPHY]Physics [physics]/Quantum Physics [quant-ph], General Materials Science, [PHYS.MECA.MEFL]Physics [physics]/Mechanics [physics]/Fluid mechanics [physics.class-ph], Composite material, [PHYS.MECA.BIOM]Physics [physics]/Mechanics [physics]/Biomechanics [physics.med-ph], [SPI.ACOU]Engineering Sciences [physics]/Acoustics [physics.class-ph], [PHYS.MECA.VIBR]Physics [physics]/Mechanics [physics]/Vibrations [physics.class-ph], Mechanical Engineering, [SPI.FLUID]Engineering Sciences [physics]/Reactive fluid environment, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Crack tip opening displacement, Numerical models, [CHIM.MATE]Chemical Sciences/Material chemistry, Paris' law, [PHYS.MECA.MSMECA]Physics [physics]/Mechanics [physics]/Materials and structures in mechanics [physics.class-ph], 021001 nanoscience & nanotechnology, Load parameters, Finite element method, CTOD (Crack Tip Opening Displacement), [PHYS.MECA.ACOU]Physics [physics]/Mechanics [physics]/Acoustics [physics.class-ph], [SPI.ELEC]Engineering Sciences [physics]/Electromagnetism, 020303 mechanical engineering & transports, Amplitude, [CHIM.POLY]Chemical Sciences/Polymers, Mechanics of Materials, [PHYS.MECA.THER]Physics [physics]/Mechanics [physics]/Thermics [physics.class-ph], 0210 nano-technology, Material properties
Abstract: International audience; The plastic CTOD range, δp, which quantifies crack tip plastic deformation, is used to study fatigue crack propagation instead of the classical ΔK elastic parameter. A da/dN-δp model was defined for the 304L stainless steel. da/dN was obtained experimentally in standard CT specimens while δp was predicted numerically using the finite element method. The numerical models replicated the experimental tests in terms of geometry, material properties and loading. The da/dN-δp model was used to predict the effects of stress state, load ratio and variable amplitude loading. All the results obtained respect the trends observed in literature, attesting that the da/dN-δp model is able to produce good qualitative predictions. Additionally it was found that crack closure is a main phenomenon affecting δp, and therefore da/dN, but there is also an effect of mean stress.
Published: 2019
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4. Retrieval of aerosol components directly from satellite and ground-based measurements

Author: Doubovik, Oleg, Li, Lei, Dubovik, Oleg, Derimian, Yevgeny, Schuster, Gregory, Lapyonok, Tatyana, Litvinov, Pavel, Ducos, Fabrice, Fuertes, David, Chen, Cheng, Li, Zhengqiang, Lopatin, Anton, Torres, Benjamin, Che, Huizheng, Laboratoire d’Optique Atmosphérique - UMR 8518 (LOA), Institut national des sciences de l'Univers (INSU - CNRS)-Université de Lille-Centre National de la Recherche Scientifique (CNRS), Chinese Academy of Meteorological Sciences (CAMS), NASA Langley Research Center [Hampton] (LaRC), GRASP-SAS, Remote Sensing Developments, Chinese Academy of Sciences [Beijing] (CAS), Freescale Semiconductor, Inc., Austin, and Freescale Semiconductor, Inc., Austin TX
Subjects: Atmospheric Science, 010504 meteorology & atmospheric sciences, Chemical transport model, [SDU.STU.GP]Sciences of the Universe [physics]/Earth Sciences/Geophysics [physics.geo-ph], [SDU.STU]Sciences of the Universe [physics]/Earth Sciences, Scale (descriptive set theory), 010501 environmental sciences, 01 natural sciences, Synthetic data, lcsh:Chemistry, Physics::Atmospheric and Oceanic Physics, ComputingMilieux_MISCELLANEOUS, 0105 earth and related environmental sciences, Remote sensing, [SDU.OCEAN]Sciences of the Universe [physics]/Ocean, Atmosphere, Single-scattering albedo, lcsh:QC1-999, AERONET, Aerosol, lcsh:QD1-999, [SDU]Sciences of the Universe [physics], [SDE]Environmental Sciences, Environmental science, Satellite, Refractive index, lcsh:Physics
Abstract: This study presents a novel methodology for the remote monitoring of aerosol components over large spatial and temporal domains. The concept is realized within the GRASP (Generalized Retrieval of Aerosol and Surface Properties) algorithm to directly infer aerosol components from the measured radiances. The observed aerosols are assumed to be mixtures of hydrated soluble particles embedded with black carbon, brown carbon, iron oxide, and other (non-absorbing) insoluble inclusions. The complex refractive indices of the dry components are fixed a priori (although the refractive index of the soluble host is allowed to vary with hydration), and the complex refractive indices of the mixture are computed using mixing rules. The volume fractions of these components are derived along with the size distribution and the fraction of spherical particles, as well as the spectral surface reflectance in cases when the satellite data are inverted. The retrieval is implemented as a statistically optimized fit in a continuous space of solutions. This contrasts with most conventional approaches in which the type of aerosol is either associated with a pre-assumed aerosol model that is included in a set of look-up tables, or determined from the analysis of the retrieved aerosol optical parameters (e.g., single scattering albedo, refractive index, among others, provided by the AERONET retrieval algorithm); here, we retrieve the aerosol components explicitly. The approach also bridges directly to the quantities used in global chemical transport models. We first tested the approach with synthetic data to estimate the uncertainty, and then applied it to real ground-based AERONET and spaceborne POLDER/PARASOL observations; thus, the study presents a first attempt to derive aerosol components from satellite observations specifically tied to global chemical transport model quantities. Our results indicate aerosol optical characteristics that are highly consistent with standard products (e.g., R of ∼0.9 for aerosol optical thickness) and demonstrate an ability to separate intrinsic optical properties of fine- and coarse-sized aerosols. We applied our method to POLDER/PARASOL radiances on the global scale and obtained spatial and temporal patterns of the aerosol components that agree well with existing knowledge on aerosol sources and transport features. Finally, we discuss limitations and perspectives of this new technique.
Published: 2019
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5. Prediction of Long-term Immunity of a Phase-Locked Loop

Author: B. Vrignon, B. Li, C. Lemoine, S. Ben Dhia, Alexandre Boyer, Équipe Énergie et Systèmes Embarqués (LAAS-ESE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Institute of Microelectronics, Chinese Academy of Sciences [Beijing] (CAS), Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT), Freescale Semiconductor, Freescale semiconductor, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, and Institut National des Sciences Appliquées (INSA)
Subjects: circuit aging, Engineering, Circuit design, Integrated circuits, Long term immunity, Integrated circuit design, 02 engineering and technology, Integrated circuit, 01 natural sciences, Electromagnetic interference, law.invention, Reliability (semiconductor), law, Control theory, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Electrical and Electronic Engineering, immunity modelling, 010302 applied physics, reliability, business.industry, Transistor, 020206 networking & telecommunications, [SPI.TRON]Engineering Sciences [physics]/Electronics, Phase-locked loop, susceptibiity to electromagnetic interferences, business, Degradation (telecommunications)
Abstract: International audience; Degradation mechanisms accelerated by harsh conditions (high temperature, electrical stress) can affect circuit performances. Submitted to electromagnetic interferences, aged components can become more susceptible, which stirs up questions about the safety level of the final application. Unfortunately, the impact of circuit aging on its susceptibility level remains under evaluated and is not taken into account at circuit design level. This paper presents a first attempt of a modeling methodology aiming at predicting the impact of circuit aging on the susceptibility to electromagnetic interferences. This methodology is applied to model and explain the measured variations of the susceptibility level of phase-locked loop after an accelerated-life test.
Published: 2012
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6. Analysis of the diffraction pattern for optimal assist feature placement

Author: Emek Yesilada, G. Kerrien, Catherine Martinelli, Florent Vautrin, Laurent Le Cam, Christophe Couderc, Jerome Belledent, Frank Sundermann, Patrick Schiavone, Franck Foussadier, Yorick Trouiller, Jonathan Planchot, Jean-Christophe Urbani, Patrick Montgomery, Mazen Saied, Frederic Robert, Amandine Borjon, Bill Willkinson, Yves Rody, Christian Gardin, Laboratoire des technologies de la microélectronique (LTM), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS), Philips France Semiconducteurs, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Freescale Semiconductor (FREESCALE SEMICONDUCTOR), Freescale semiconductor, STMicroelectronics [Crolles] (ST-CROLLES), Freescale Semiconductor Inc., NXP Semiconductors, and Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)
Subjects: Diffraction, Depth of focus, Computer science, SVM, Process window, 02 engineering and technology, 01 natural sciences, 010309 optics, Optics, Optical proximity correction, Position (vector), 0103 physical sciences, Reticle, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, business.industry, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, ORC, Failure prediction, Feature (computer vision), 0210 nano-technology, business, OPC, Exposure latitude, Algorithm
Abstract: International audience; Assist features (AF) are an essential component of reticle enhancement techniques. Their use is indispensable in sub-100 nm technologies to ensure a maximum process window (PW) across chip, especially for critical levels. Indeed, AF, which can be binary, attenuated or phase-shifted, help in providing a larger PW to the features they assist when they are used in conjunction with off-axis illumination. The depth of focus (DOF) of an isolated structure is improved by the presence of AF by providing to the optical system a diffraction pattern close to the diffraction pattern of a dense structure. The resulting DOF and exposure latitude (EL) are dependent on the relative position of the AF from the main feature. Moreover, the PW varies while inserting one, two or more AF. The relative position of each influences the results. In this paper, a method will be detailed to optimise the placement of the AF. For the purpose of this study, the diffraction pattern induced by the insertion of one or several AF is analysed in frequency space. This analysis details the evolution of the intensity of even and odd orders during the insertion of AF. The calculation of the optimum placement is detailed, and the DOF resulting from the insertion of one or more AF is also presented.
Published: 2007
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7. Preliminary study of Automatic Control Gain loop subjected to pulse-modulated radiofrequency interference

Author: J. Raoult, A. Doridant, P. Hoffmann, J-J. Laurin, S. Jarrix, FreeScale Semiconductor Inc., Freescale Semiconductor Inc., École Polytechnique de Montréal (EPM), Radiations et composants (RADIAC), Institut d’Electronique et des Systèmes (IES), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), GRAMAT (DAM/GRAMAT), Direction des Applications Militaires (DAM), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)
Subjects: 010302 applied physics, Log amplifier, Pulse repetition frequency, Materials science, Automatic Generation Control, Pulse (signal processing), 020206 networking & telecommunications, 02 engineering and technology, Interference (wave propagation), 01 natural sciences, Electromagnetic interference, [SPI.TRON]Engineering Sciences [physics]/Electronics, stomatognathic diseases, Control theory, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Automatic gain control, Transient response
Abstract: International audience; The paper presents a detailed study of the dynamic response of an Automatic Gain Control loop (AGC loop) exposed to pulsed radiofrequency interference. It is shown that the most significant effect is an increase of the RF output level of the AGC that is strongly dependent on the pulse repetition frequency, the effect being less pronounced as the repetition frequency increases. It is demonstrated that this is related to the transient response of the logarithmic amplifier, which can be controlled by decoupling capacitors.
Published: 2015
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8. Modeling Magnetic Near-Field Injection at Silicon Die Level

Author: B. Vrignon, A. Boyer, Manuel Cavarroc, Équipe Énergie et Systèmes Embarqués (LAAS-ESE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Freescale Semiconductor, Freescale semiconductor, Service Instrumentation Conception Caractérisation (LAAS-I2C), ANR-12-INSE-0005,E-MATA HARI,Analyse électromagnétique, déchiffrement et ingénierie inverse de circuits intégrés(2012), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées
Subjects: Materials science, Near and far field, 02 engineering and technology, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, electromagnetic attack, on-chip sensor, susceptibility, law.invention, Computer Science::Hardware Architecture, law, 0202 electrical engineering, electronic engineering, information engineering, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, business.industry, 020208 electrical & electronic engineering, Electrical engineering, integrated circuit, 020206 networking & telecommunications, modeling, Condensed Matter Physics, Chip, Atomic and Molecular Physics, and Optics, Magnetic field, [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI.ELEC]Engineering Sciences [physics]/Electromagnetism, near-field injection, business, Voltage
Abstract: International audience; Near-field injection at silicon die level is a promising application for various area such as the analyses of integrated circuit (IC) susceptibility to electromagnetic interferences and security for cryptographic applications. This paper presents a first attempt to simulate the voltage induced on integrated circuit interconnects by a magnetic field probe. The validation of the simulation results is based on near-field injection performed on a test chip containing various types of interconnects and on-chip voltage sensors.
Published: 2015
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9. Electromagnetic near field injection model on integrated circuit

Author: Omarouayache, Rachid, Raoult, Jérémy, Payet, Pierre, Chusseau, Laurent, Vrignon, Bertrand, Doridant, Adrien, Boyer, Alexandre, Institut d’Electronique et des Systèmes (IES), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Radiations et composants (RADIAC), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Freescale Semiconductor, Freescale semiconductor, Freescale Semiconductor (Freescale), Équipe Énergie et Systèmes Embarqués (LAAS-ESE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)
Subjects: [SPI.ELEC]Engineering Sciences [physics]/Electromagnetism, ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract: International audience
Published: 2015

10. Modèle d'injection électromagnétique en champ proche sur circuit intégré

Author: Omarouayache, Rachid, Raoult, Jérémy, Payet, Pierre, Chusseau, Laurent, Vrignon, Bertrand, Shepherd, John, Boyer, Alexandre, Institut d’Electronique et des Systèmes (IES), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Radiations et composants (RADIAC), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Freescale Semiconductor, Freescale semiconductor, Équipe Énergie et Systèmes Embarqués (LAAS-ESE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)
Subjects: [SPI.ELEC]Engineering Sciences [physics]/Electromagnetism, ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract: National audience
Published: 2015

11. Near-Field Injection At Die Level

Author: Boyer, Alexandre, Vrignon, B, Cavarroc, Manuel, Shepherd, J, Équipe Énergie et Systèmes Embarqués (LAAS-ESE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Freescale Semiconductor, Freescale semiconductor, Service Instrumentation Conception Caractérisation (LAAS-I2C), ANR-12-INSE-0005,E-MATA HARI,Analyse électromagnétique, déchiffrement et ingénierie inverse de circuits intégrés(2012), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées
Subjects: Computer Science::Hardware Architecture, [SPI.ELEC]Engineering Sciences [physics]/Electromagnetism, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract: International audience; Near-field injection is a promising method in order to induce local faults in integrated circuits. This paper aims at proposing a model of the coupling between the injection probe and the circuit under test. This study relies on measurements performed on a test chip by on-chip voltage sensors. I. INTRODUCTION Near-field injection constitutes a promising method for various applications such as electromagnetic attacks on secured circuits or investigations of integrated circuits (ICs) susceptibility to electromagnetic disturbances [1]. The injection at die level offers the advantage to locate precisely the origin of the faults induced by the coupling of the near-field disturbance. This paper attempts to clarify the nature of the coupling between the injection probe and the circuit under test by the development of a model of the coupling. This study relies on near-field injection measurements performed on a test chip which integrates several on-chip voltage sensors for accurate characterization in high frequency of the voltage induced along circuit interconnects.
Published: 2015

12. Prediction of Aging Impact on Electromagnetic Susceptibility of an Operational Amplifier

Author: A. Boyer, Sonia Ben Dhia, He Huang, B. Vrignon, Équipe Énergie et Systèmes Embarqués (LAAS-ESE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Freescale Semiconductor, Freescale semiconductor, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées
Subjects: 010302 applied physics, EKV MOSFET Model, Computer science, Electromagnetic susceptibility, Electromagnetic compatibility, 020206 networking & telecommunications, 02 engineering and technology, 01 natural sciences, Electromagnetic interference, law.invention, [SPI.TRON]Engineering Sciences [physics]/Electronics, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Cmos operational amplifier, Electronic engineering, Operational amplifier
Abstract: International audience; This paper deals with the impact of aging on the electromagnetic susceptibility level of a CMOS operational amplifier (opamp). The aging impact can be modelled by the variation of several parameters of the MOSFET model, to predict the evolution of electromagnetic susceptibility (EMS) of the opamp block during the aging process. I. INTRODUCTION The increasing use of high speed and complex electronic systems makes the electromagnetic compatibility (EMC) an important issue for the electronic manufacturers [1]. Some experimental results show the significant reduced EMC evolution after aging stress [2]. Thus how to ensure EMC during the whole lifetime of IC products, which is called electromagnetic robustness (EMR), becomes a new study in the recent years. As presented in only few works, the simulation can be used to predict the long-term EMC behaviour. For example, in [3], the increase of the electromagnetic emission of a DC-DC converter after thermal stress is modeled, which is associated to the degradation of filtering passive devices. In [4], the simulation results confirm the evolution of the EMS of a phase-locked loop (PLL) before and after aging. The aging affects the threshold voltage and the mobility of the MOSFET of the PLL. However, in these case studies only two statuses (the device before and after a period of aging) are measured and simulated. Thus there is a lack of more precise insight about the evolution of the different phases during the whole aging time. As a common electronic block, the operational amplifier is very susceptible to the external electromagnetic interference (EMI). The coupling of EMI on opamp inputs and power supply leads to a distortion of the output voltage, especially the generation of a voltage offset on its output which is harmful and hard to remove [5], [6]. In this study, with the aging stress injected in several parts of the amplifier, a worse DC output offset value at several frequencies could be observed, that means the device becomes more susceptible to the EMI with the aging. So the prediction of EMS evolution becomes important to help the IC designers to prevent EMC failure during the ICs' lifetime.
Published: 2015

13. Susceptibility Analysis of an Operational Amplifier Using On-Chip Measurement

Author: A. Boyer, S. Ben Dhia, He Huang, B. Vrignon, Équipe Énergie et Systèmes Embarqués (LAAS-ESE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Freescale Semiconductor, Freescale semiconductor, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)
Subjects: Engineering, business.industry, on-chip measurement, Electrical engineering, integrated circuit, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, Signal, Electromagnetic interference, conducted susceptibility, law.invention, [SPI.TRON]Engineering Sciences [physics]/Electronics, law, Operational amplifier, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, System on a chip, Transient response, Time domain, business, Voltage
Abstract: International audience; This paper presents an electromagnetic immunity study of a simple operational amplifier by using the on-chip measurement. With the technology of on-chip non-invasive sensor, the internal inaccessible signal (voltage/current) can be obtained accurately in time domain. This approach grants a good insight in the internal transient response caused by the external electromagnetic interference. The validity of the on-chip measurement results is discussed comparing with the off-chip measurement and simulation.
Published: 2014

14. Evaluation of the Near-Field Injection Method at Integrated Circuit Level

Author: B. Vrignon, M. Cavarroc, A. Boyer, John Shepherd, Équipe Énergie et Systèmes Embarqués (LAAS-ESE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Freescale Semiconductor, Freescale semiconductor, Service Instrumentation Conception Caractérisation (LAAS-I2C), ANR-12-INSE-0005,E-MATA HARI,Analyse électromagnétique, déchiffrement et ingénierie inverse de circuits intégrés(2012), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)
Subjects: Engineering, business.industry, near-field scan injection, 020208 electrical & electronic engineering, Induced voltage, Electrical engineering, 020206 networking & telecommunications, Near and far field, 02 engineering and technology, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, electromagnetic attack, susceptibility, law.invention, [SPI.TRON]Engineering Sciences [physics]/Electronics, Computer Science::Hardware Architecture, law, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, business, Electronic circuit, Voltage
Abstract: International audience; Near-field injection is a promising method in order to induce local faults in integrated circuits. This method can be used for various applications such as electromagnetic attacks on secured circuits or susceptibility investigations. This paper aims at evaluating the ability of near-field scan injection to induce local disturbances in integrated circuits. The study relies on measurements performed by on-chip voltage sensors, which provide an accurate method to characterize the induced voltage fluctuations.
Published: 2014

15. Modeling and Simulation of LDO Voltage Regulator Susceptibility to Conducted EMI

Author: Rongjun Shen, Jianfei Wu, Jiancheng Li, Sonia Ben Dhia, Etienne Sicard, B. Vrignon, Alexandre Boyer, College of Life and Health Sciences, Institute of Neuroscience, Équipe Énergie et Systèmes Embarqués (LAAS-ESE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Freescale Semiconductor, Freescale semiconductor, Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT), Multimedia Research Center (MRC), University of Alberta, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Institut National des Sciences Appliquées (INSA), Laboratoire Toulousain de Technologie et d'Ingénierie des Systèmes (LATTIS), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J)-IUT Toulouse 2 Blagnac, School of Electronic Science and Engineering, National Key Laboratory for Parallel and Distributed Processing [Changsha], National University of Defense Technology [China]-National University of Defense Technology [China], Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), and Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1)
Subjects: Conducted electromagnetic interference, Engineering, Low-dropout regulator, business.industry, Voltage regulator, Condensed Matter Physics, Chip, Atomic and Molecular Physics, and Optics, Electromagnetic interference, law.invention, [SPI.TRON]Engineering Sciences [physics]/Electronics, Modeling and simulation, [SPI.ELEC]Engineering Sciences [physics]/Electromagnetism, Capacitor, law, EMI, Electronic engineering, Electrical and Electronic Engineering, business
Abstract: International audience; This paper presents a methodology dedicated to mod-eling and simulation of low-dropout (LDO) voltage regulator susceptibility to conducted electromagnetic interference (EMI). A test chip with a simple LDO structure was designed for EMC test and analysis. A transistor-level model, validated by functional tests, Z-parameter characterization and direct power injection (DPI) measurements, is used to predict the immunity of the LDO regulator. Different levels of model extraction reveal the weight contributions of subcircuits and parasitic elements on immunity issues. The DPI measurement results show a good fit with model prediction up to 1 GHz. Index Terms—Direct power injection (DPI), electromagnetic interference (EMI), interference propagation, low-dropout (LDO) voltage regulator, parasitic elements, susceptibility, Z-parameter.
Published: 2014
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16. Effect of etch pattern transfer on local overlay (OVL) margin in 28nm gate integration

Author: Oehrlein, Gottlieb, Lin, Qinghuang, Zhang, Ying, Ros, Onintza, Gouraud, Pascal, Le-Gratiet, Bertrand, Gardin, Christian, Ducote, Julien, Pargon, Erwine, State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources [Beijing] (NCEPU), North China Electric Power University, STMicroelectronics, Freescale Semiconductor (FREESCALE SEMICONDUCTOR), Freescale semiconductor, STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire des technologies de la microélectronique (LTM), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS), Palmipèdes à Foie Gras (UEPFG), Institut National de la Recherche Agronomique (INRA), Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'Énergie Atomique et aux Énergies Alternatives (CEA) - Grenoble-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), and Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)
Subjects: [PHYS]Physics [physics], 010302 applied physics, business.industry, Nanotechnology, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Overlay, 021001 nanoscience & nanotechnology, 01 natural sciences, Resist, Stack (abstract data type), Distortion, 0103 physical sciences, Process integration, Hardware_INTEGRATEDCIRCUITS, Optoelectronics, Process control, 0210 nano-technology, Metal gate, business, Lithography, ComputingMilieux_MISCELLANEOUS
Abstract: One of the main process control challenges in logic process integration is the contact to gate overlay. Usual ways for overlay control are run to run corrections (high order process corrections) and scanner control (baseliner control loop) to keep overlay within the very tight ITRS specifications, i.e. 7nm mean+3sigma. It is known that process integration can lead to specific overlay distortion (CMP, thermal treatment etc…) which are usually partly handled by high order process corrections at scanner level. In addition, recently we have shown that etch process can also lead to local overlay distortions, especially at the wafer edge [1]. In this paper we look into another overlay distortion level which can happen during etch processes. We will show that resist cure steps during gate patterning affect lithography defined profiles leading to local pattern shifting. This so called gate shifting has been characterized by etch process partitioning during a typical high-K metal gate patterning with spinon carbon and Si-ARC lithography stack onto a high-K metal gate / poly-silicon / oxide hard mask stack. We will show that modifying the resist-cure / Si-ARC open chemistry strongly contributes to gate shifting reduction by an equivalent of 40% overlay margin reduction.
Published: 2014
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17. Universal mechanisms of Al metallization ageing in power MOSFET devices

Author: Marc Legros, Thomas Mazeaud, Colette Levade, Donatien Martineau, Philippe Dupuy, Centre d'élaboration de matériaux et d'études structurales (CEMES), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Chimie de Toulouse (ICT-FR 2599), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut de Chimie du CNRS (INC)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Institut de Chimie du CNRS (INC)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Freescale Semiconductor, Toulouse, Freescale semiconductor, Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut de Chimie de Toulouse (ICT), Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), and Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)
Subjects: Materials science, 02 engineering and technology, Plasticity, Al-metallization, 01 natural sciences, Thermal expansion, Degradation, FIB, Electrical resistivity and conductivity, 0103 physical sciences, Forensic engineering, Grain boundary diffusion coefficient, Metallizing, Grain-boundary diffusion, Structural modifications, Electrical and Electronic Engineering, Power MOSFET, Safety, Risk, Reliability and Quality, MOSFET devices, Plastic deformation, 010302 applied physics, [PHYS]Physics [physics], Coefficients of thermal expansions, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Engineering physics, Degradation mechanism, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Universal mechanisms, Grain boundary grooving, Grain boundaries, Grain boundary, 0210 nano-technology, Layer (electronics), Transmission electron microscopy, Automotive industry, Aluminum
Abstract: cited By 10; International audience; Power MOSFET devices are extensively used in the automotive industry, but their modes of ageing are still poorly understood. Here we focus on the physical degradation mechanisms that occur in the upper Al-based metallization layer (source). This layer undergoes thermo-mechanical structural modifications due to the combination of electrical pulses and differences between the various coefficients of thermal expansion. Using electronic and ionic microscopy, we show that ageing can be divided in 2 phases where dislocation-based plasticity and then grain boundary diffusion become predominant. As a result, grain boundary grooving and surface roughening follows a partial division of the later in disconnected Al grains. Such a degradation of the metallization has been widely observed in various devices. It may lead to the observed augmentation of resistivity and also to the focusing of the various current paths, promoting hot spots and subsequent failure.
Published: 2014
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18. Reliability of power MOSFET-based smart switches under normal and extreme conditions for 24 V battery system applications

Author: Rostaing, Gilles, Berkani, Mounira, Lefebvre, Stéphane, Khatir, Zoubir, Dupuy, Philippe, Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), Université Paris-Est Créteil Val-de-Marne - Paris 12 (UPEC UP12), Laboratoire des Technologies Nouvelles (IFSTTAR/LTN), Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR), FREESCALE Semiconductor Toulouse, Freescale, Freescale-Freescale, Laboratoire des Technologies Nouvelles (IFSTTAR/COSYS/LTN), Freescale Semiconductor, and Lefebvre, Stéphane
Subjects: [SPI]Engineering Sciences [physics], [SPI] Engineering Sciences [physics], Smart power, [SPI.NRJ]Engineering Sciences [physics]/Electric power, extreme conditions, relaibility, ageing tests, ComputingMilieux_MISCELLANEOUS, [SPI.NRJ] Engineering Sciences [physics]/Electric power, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract: International audience; This study aims to assess the reliability of smart converters for applications using 24 V batteries. It compares degradation effects and lifetime durations for similar dissipated energies when these smart power switches are subjected to normal and extreme protection test conditions. Three experimental ageing tests have been performed: (i) ageing tests under normal protection mode, (ii) ageing tests under repetitive inductive avalanche switching and (iii) ageing tests under repetitive short-circuit. Evolution of several electrical parameters such as on-state resistance; threshold voltage and saturation current have been monitored. Tested devices under normal condition and under repetitive inductive avalanche have failed after about the same number of cycles with the same dissipated energy. However, several results show a significant decrease of the lifetime under repetitive short-circuit tests for a similar dissipated energy.
Published: 2013

19. Switching Optimization of WBG Power Devices on Inverter Leg

Author: Rossignol, Timothé, RICHARDEAU, Frédéric, Blaquière, Jean-Marc, Risaletto, Damien, Senghor, F., Cousineau, Marc, AULAGNIER, GUILLAUME, Cousineau, Marc, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Technocentre Renault [Guyancourt], RENAULT, University of Toulouse, Convertisseurs Statiques (LAPLACE-CS), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Centre National de la Recherche Scientifique (CNRS), Institut National Polytechnique de Toulouse (INPT-ENSEEIHT), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées, Freescale Semiconductor (Freescale), and Freescale semiconductor
Subjects: [SPI.NRJ]Engineering Sciences [physics]/Electric power, Switching optimization, Hardware_INTEGRATEDCIRCUITS, Wide band gap devices, Inverter leg, Hardware_PERFORMANCEANDRELIABILITY, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract: International audience; In this paper the authors are interested by the switching optimisation of a SiC Power MOSFET in an inverter leg. The authors explain their efforts to build a test-bench that allows the extremely fast switching measurement of this WBG (Wide Band-Gap) component. Then trade-off curves between the dv/dt versus the switching energy are presented. The parameters are the external gate resistor and an additional gate-drain capacitor. Finally, basic dv/dt models are proposed and compared with the experimental results.
Published: 2013

20. A New Approach to Modeling the Impact of EMI on MOSFET DC Behavior

Author: B. Vrignon, Alexandre Boyer, Raul Fernandez-Garcia, Sonia Bendhia, Ignacio Gil, Universitat Politècnica de Catalunya [Barcelona] (UPC), Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Freescale Semiconductor, Freescale semiconductor, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées
Subjects: Engineering, Electrical modelling, 02 engineering and technology, 01 natural sciences, 7. Clean energy, Electromagnetic interference, Computer Science::Hardware Architecture, MOSFET, EMI, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Electrical and Electronic Engineering, Drain current, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, Mathematics::History and Overview, Electrical engineering, Current source, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, Electronic, Optical and Magnetic Materials, [SPI.TRON]Engineering Sciences [physics]/Electronics, Equivalent circuit, business, Electromagnetic Compatibility (EMC), Voltage
Abstract: 3 pages; International audience; A simple analytical model to predict the DC MOSFET behaviour under electromagnetic interference (EMI) is presented. The model is able to describe the MOSFET performance in linear and saturation regime under EMI disturbance applied on the gate. The model consists of a unique simple equivalent circuit based on a voltage dependant current source and a reduced number of parameters which can accurately predict the drift on the drain current due to the EMI source. The analytical approach has been validated by means of electric simulation and measurements and can be easily introduced in circuit simulators. The proposed modelling technique combined with the nth-power law model of the MOSFET without EMI, significantly improves its accuracy in comparison with the nth-power law directly applied to a MOSFET under EMI impact.
Published: 2011

21. An On-Chip Sensor for Time Domain Characterization of Electromagnetic Interferences

Author: Boyer, Alexandre, Ben Dhia, Sonia, Lemoine, Christophe, Vrignon, Bertrand, Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Laboratoire Toulousain de Technologie et d'Ingénierie des Systèmes (LATTIS), Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J)-IUT Toulouse 2 Blagnac, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse - Jean Jaurès (UT2J), Freescale Semiconductor, Freescale semiconductor, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-IUT Toulouse 2 Blagnac, Université Toulouse - Jean Jaurès (UT2J), and Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J)
Subjects: Hardware_INTEGRATEDCIRCUITS, onchip measurement, Hardware_PERFORMANCEANDRELIABILITY, integrated circuits, conducted susceptibility, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract: International audience; With the growing concerns about susceptibility of integrated circuits to electromagnetic interferences, the need for accurate prediction tools and models to reduce risks of noncompliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation. This paper presents an on-chip noise sensor dedicated to the time-domain measurement of voltage fluctuations induced by interference coupling.
Published: 2011

22. Construction and Evaluation of the Susceptibility Model of an Integrated Phase-Locked Loop

Author: Boyer, Alexandre, Ben Dhia, Sonia, Lemoine, Christophe, Vrignon, Bertrand, Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA), Freescale Semiconductor, Freescale semiconductor, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), and Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)
Subjects: on-chip measurement, phase-locked loop, Hardware_INTEGRATEDCIRCUITS, integrated circuit, modeling, Hardware_PERFORMANCEANDRELIABILITY, susceptibility, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract: 6 pages; International audience; Developing integrated circuit immunity models has become one of the major concerns of integrated circuits suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign process. This paper presents the development process of the susceptibility model an integrated phase-locked loop to harmonic disturbances up to 1 GHz. The model construction is based on basic circuit information and S parameter measurements. An evaluation of the model accuracy is ensured by the characterization of internal voltage fluctuations with an on-chip sensor.
Published: 2011

23. On the Precoder Design of Flat Fading MIMO Systems Equipped With MMSE Receivers: A Large-System Approach

Author: Cedric Artigue, Philippe Loubaton, Freescale Semiconductor, Freescale semiconductor, Laboratoire d'Informatique Gaspard-Monge (LIGM), Université Paris-Est Marne-la-Vallée (UPEM)-École des Ponts ParisTech (ENPC)-ESIEE Paris-Fédération de Recherche Bézout-Centre National de la Recherche Scientifique (CNRS), and Centre National de la Recherche Scientifique (CNRS)-Fédération de Recherche Bézout-ESIEE Paris-École des Ponts ParisTech (ENPC)-Université Paris-Est Marne-la-Vallée (UPEM)
Subjects: FOS: Computer and information sciences, Computer science, Covariance matrix, Computer Science - Information Theory, Information Theory (cs.IT), Transmitter, Mathematics::History and Overview, 020206 networking & telecommunications, 02 engineering and technology, Mutual information, Library and Information Sciences, Topology, Computer Science Applications, Channel state information, Approximation error, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Fading, Information Systems, Communication channel, Computer Science::Information Theory
Abstract: This paper is devoted to the design of precoders maximizing the ergodic mutual information (EMI) of bi-correlated flat fading MIMO systems equiped with MMSE receivers. The channel state information and the second order statistics of the channel are assumed available at the receiver side and at the transmitter side respectively. As the direct maximization of the EMI needs the use of non attractive algorithms, it is proposed to optimize an approximation of the EMI, introduced recently, obtained when the number of transmit and receive antennas $t$ and $r$ converge to $\infty$ at the same rate. It is established that the relative error between the actual EMI and its approximation is a $O(\frac{1}{t^{2}})$ term. It is shown that the left singular eigenvectors of the optimum precoder coincide with the eigenvectors of the transmit covariance matrix, and its singular values are solution of a certain maximization problem. Numerical experiments show that the mutual information provided by this precoder is close from what is obtained by maximizing the true EMI, but that the algorithm maximizing the approximation is much less computationally intensive., Comment: Submitted to IEEE Transactions on Information Theory
Published: 2011
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24. L'abri-sous-roche Paléolithique moyen de Mutzig, Rain (Bas-Rhin, F) : reprise des travaux

Author: Detrey, Jean, Guelat, M., Hauck, T., Rentzl, P., Etude des Civilisations de l'Antiquité (UMR 7044), Université de Haute-Alsace (UHA) Mulhouse - Colmar (Université de Haute-Alsace (UHA))-Université Marc Bloch - Strasbourg II-Centre National de la Recherche Scientifique (CNRS), Freescale Semiconductor, and Freescale Semiconductor, Schatzbogen
Subjects: [SHS.ARCHEO]Humanities and Social Sciences/Archaeology and Prehistory, abri-sous-roche, Mutzig, Paléolithique, ComputingMilieux_MISCELLANEOUS
Abstract: International audience
Published: 2010

25. Characterization of the Evolution of IC Emissions after Accelerated Aging

Author: L. Guillot, S. Ben Dhia, Alexandre Boyer, A.C. Ndoye, B. Vrignon, Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT), Laboratoire Toulousain de Technologie et d'Ingénierie des Systèmes (LATTIS), Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-IUT Toulouse 2 Blagnac, Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Freescale Semiconductor, Freescale semiconductor, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-IUT Toulouse 2 Blagnac, and Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse - Jean Jaurès (UT2J)
Subjects: Engineering, Automotive industry, 02 engineering and technology, Integrated circuit, 01 natural sciences, Automotive engineering, Integrated circuit testing, law.invention, Reliability (semiconductor), law, Power electronics, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Electrical and Electronic Engineering, electromagnetic compatibility, Electronic circuit, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, Electromagnetic compatibility, conducted emission, Condensed Matter Physics, Accelerated aging, aging effects, Atomic and Molecular Physics, and Optics, [SPI.TRON]Engineering Sciences [physics]/Electronics, visual_art, Electronic component, visual_art.visual_art_medium, business
Abstract: 9 pages; International audience; With the evolving technological development of integrated circuits (ICs), ensuring electromagnetic compatibility (EMC) is becoming a serious challenge for electronic circuit and system manufacturers. Although electronic components must pass a set of EMC tests to ensure safe operations, the evolution over time of EMC is not characterized and cannot be accurately forecast. This paper presents an original study about the consequences of the aging of circuits on electromagnetic emission. Different types of standard applicative and accelerated-life tests are applied on a mixed power circuit dedicated to automotive applications. Its conducted emission is measured before and after these tests showing variations in EMC performances. Comparisons between each type of aging procedure show that the emission level of the circuit under test is affected differently.
Published: 2009

26. Shared resources high-level modeling in embedded systems using virtual nodes

Author: Renaud Pacalet, Chafic Jaber, Andreas Kanstein, Amer Baghdadi, Ludovic Apvrille, Département Electronique ( ELEC ), Université européenne de Bretagne ( UEB ) -Télécom Bretagne-Institut Mines-Télécom [Paris], Freescale Semiconductor ( Freescale ), Freescale semiconductor, Télécom ParisTech, Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192) ( Lab-STICC ), Université européenne de Bretagne ( UEB ) -Université de Bretagne Sud ( UBS ) -Université de Brest ( UBO ) -Institut Brestois du Numérique et des Mathématiques ( IBNM ), Université de Brest ( UBO ) -Télécom Bretagne-Institut Mines-Télécom [Paris]-Centre National de la Recherche Scientifique ( CNRS ), Lab-STICC_TB_CACS_IAS, Université de Brest ( UBO ) -Télécom Bretagne-Institut Mines-Télécom [Paris]-Centre National de la Recherche Scientifique ( CNRS ) -Université européenne de Bretagne ( UEB ) -Université de Bretagne Sud ( UBS ) -Université de Brest ( UBO ) -Institut Brestois du Numérique et des Mathématiques ( IBNM ), Université de Brest ( UBO ) -Télécom Bretagne-Institut Mines-Télécom [Paris]-Centre National de la Recherche Scientifique ( CNRS ) -Département Electronique ( ELEC ), Département Electronique (ELEC), Université européenne de Bretagne - European University of Brittany (UEB)-Institut Mines-Télécom [Paris] (IMT)-Télécom Bretagne, Freescale Semiconductor (Freescale), Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192) (Lab-STICC), Université européenne de Bretagne - European University of Brittany (UEB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-Institut Brestois du Numérique et des Mathématiques (IBNM), Université de Brest (UBO)-Télécom Bretagne-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS), and Université de Brest (UBO)-Télécom Bretagne-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université européenne de Bretagne - European University of Brittany (UEB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-Institut Brestois du Numérique et des Mathématiques (IBNM)
Subjects: 010302 applied physics, business.industry, Computer science, Node (networking), Time to market, 02 engineering and technology, 01 natural sciences, Architecture exploraition, 020202 computer hardware & architecture, UML, Hardware/software co-design, Unified Modeling Language, SystemC, High-level synthesis, Embedded system, 0103 physical sciences, System on chip, Shared resources modeling, 0202 electrical engineering, electronic engineering, information engineering, Use case, System on a chip, business, computer, computer.programming_language, Abstraction (linguistics)
Abstract: International audience; The increasing complexity of system-on-chip design and shorter time to market constraints has stimulated systems designers to investigate performance characteristics of the final system implementation in the early design stages, by means of modeling the design at a high level of abstraction. This paper presents the virtual node concept for modeling the shared resources of a system-on-chip, therefore specifically dedicated to the study of the impact of shared resources contention on the overall systems performance, which is often defined by concurrent use cases. The overall approach is based on using a specific UML modeling profile and a SystemC-based simulator to execute models and analyze their performance.
Published: 2009

27. Size effects on varistor properties made from zinc oxide nanoparticles by low temperature spark plasma sintering

Author: Saint Macary, Lena, Kahn, Myrtil L., Estournès, Claude, Fau, Pierre, Trémouilles, David, Bafleur, Marise, Renaud, Philippe, Chaudret, Bruno, Freescale Semiconducteurs, Laboratoire de chimie de coordination (LCC), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut de Chimie de Toulouse (ICT-FR 2599), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS), Centre interuniversitaire de recherche et d'ingenierie des matériaux (CIRIMAT), Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Institut de Chimie du CNRS (INC), Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Laboratoire commun LISPA avec Freescale Semiconductor, Freescale Semiconductor, Institut de Chimie de Toulouse (ICT), Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS), Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), and Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole)
Subjects: Zinc oxide, Spark plasma sintering, Varistor, Nanoparticles, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Organometallic
Abstract: International audience; Conditions for the elaboration of nanostructured varistors by Spark Plasma Sintering (SPS) are investigated, using 8 nm zinc oxide nanoparticles synthesized following an organometallic approach. A binary system constituted of zinc oxide and bismuth oxides nanoparticles is used for this purpose. It is synthesized at room temperature in an organic solution through the hydrolysis of dicyclohexylzinc and bismuth acetate precursors. Sintering of this material is performed by SPS at various temperatures and dwell times. The determination of the microstructure and the chemical composition of the as prepared ceramics are based on Scanning Electron Microscopy (SEM) and X-Ray Diffraction (XRD) analysis. The non linear electrical characteristics are evidenced by current-voltage (I-V) measurements. The breakdown voltage of these nanostructured varistors strongly depends on grain sizes. The results show for the first time that, nanostructured varistors are obtained by SPS at sintering temperatures ranging from 550 to 600°C.
Published: 2009

28. Thin film characterization by total reflection x-ray fluorescence

Author: Adrien Danel, Tifenn Decorps, Maria-Luisa Calvo-Muñoz, Charles Geoffroy, Marc Veillerot, Motoyuki Yamagami, Emmanuel Nolot, Sandrine Lhostis, Jean-Michel Hartmann, Segolene Olivier, Hiroshi Kohno, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Freescale Semiconductor, Freescale semiconductor, Rigaku Corporation, and Elexience
Subjects: Materials science, Composition analysis, X-ray fluorescence, Substrate (electronics), 01 natural sciences, Analytical Chemistry, Optics, 0103 physical sciences, Wafer, Thin film, Instrumentation, Saturation (magnetic), Spectroscopy, 010302 applied physics, Total internal reflection, Silicon wafer, business.industry, 010401 analytical chemistry, [CHIM.MATE]Chemical Sciences/Material chemistry, Dead time, Atomic and Molecular Physics, and Optics, 0104 chemical sciences, Metrology, TXRF, business
Abstract: International audience; Sensitive and accurate characterization of films thinner than a few nm used in nanoelectronics represents a challenge for many conventional production metrology tools. With capabilities in the 1010 at/cm2, methods usually dedicated to contamination analysis appear promising, especially Total-reflection X-Ray Fluorescence (TXRF). This study shows that under usual configuration for contamination analysis, with incident angle smaller than the critical angle of the substrate, TXRF signal saturation occurs very rapidly for dense films (below 0.5 nm for HfO2 films on Si wafers using a 9.67 keV excitation at 0.5°). Increasing the incident angle, the range of linear results can be extended, but on the other hand, the TXRF sensitivity is degraded because of a strong increase of the measurement dead time. On HfO2 films grown on Si wafers, an incident angle of 0.32° corresponding to a dead time of 95% was used to achieve linear analysis up to 2 nm. Composition analysis by TXRF, and especially the detection of minor elements into thin films, requires the use of a specific incident angle to optimize sensitivity. Although quantitative analyses might require specific calibration, this work shows on Co–based films that the ratio between minor elements (W, P, Mo) and Co taking into account their relative sensitivity factors is a good direct reading of the composition
Published: 2008
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29. Modeling the Electromagnetic Emission of a Microcontroller Using a Single Model

Author: C. Labussiere-Dorgan, S. Bendhia, Etienne Sicard, C. Lochot, B. Vrignon, H.J. Quaresma, Junwu Tao, Centre d'essais Aéronautique de Toulouse, Équipe Énergie et Systèmes Embarqués (LAAS-ESE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Laboratoire Toulousain de Technologie et d'Ingénierie des Systèmes (LATTIS), Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-IUT Toulouse 2 Blagnac, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse - Jean Jaurès (UT2J), Groupe de Recherche en Electromagnétisme (LAPLACE-GRE), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Freescale Semiconductor, Freescale semiconductor, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-IUT Toulouse 2 Blagnac, Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), and Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP)
Subjects: Engineering, 02 engineering and technology, Integrated circuit design, Integrated circuit, Effective radiated power, 7. Clean energy, law.invention, Computer Science::Hardware Architecture, [SPI]Engineering Sciences [physics], law, Electromagnetism, Computer Science::Multimedia, 0202 electrical engineering, electronic engineering, information engineering, Scattering parameters, Electronic engineering, Electrical and Electronic Engineering, business.industry, 020208 electrical & electronic engineering, Electromagnetic compatibility, 020206 networking & telecommunications, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Transverse mode, [SPI.TRON]Engineering Sciences [physics]/Electronics, Microcontroller, [SPI.ELEC]Engineering Sciences [physics]/Electromagnetism, business
Abstract: International audience; This paper presents a methodology for building an integrated circuit behavioral model that enables the prediction of its electromagnetic (EM) emissions up to several gigahertz. The model, built upon S-parameter characterization and conducted emission measurements, is used to predict the EM emissions of a commercial 16-bit microcontroller. The emission measurements are performed according to several EM compatibility standards, namely, 1 Omega /150 Omega , surface scan, and transverse EM/gigahertz transverse EM (GTEM) method, and their results show an excellent fit with model predictions.
Published: 2008
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30. A NEW METHODOLOGY FOR EXTRACTION OF DYNAMIC COMPACT THERMAL MODELS

Author: C. Barbot, F. Madrid, J-M. Dorkel, W. Habra, Philippe Dupuy, P. Tounsi, Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Freescale Semiconductor, Toulouse, Freescale semiconductor, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)
Subjects: 010302 applied physics, Coupling, Computer science, 020208 electrical & electronic engineering, FOS: Physical sciences, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 7. Clean energy, 01 natural sciences, General Physics (physics.gen-ph), Physics - General Physics, Power electronics, electro-thermal Simulation, Thermal Modelling and Investigation of Packages, 0103 physical sciences, Thermal, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, [PHYS.COND.CM-MS]Physics [physics]/Condensed Matter [cond-mat]/Materials Science [cond-mat.mtrl-sci], Extraction methods, Point (geometry), Extraction (military), Transient (oscillation), Thermal model
Abstract: An innovative and accurate dynamic Compact Thermal Model extraction method is proposed for multi-chip power electronics systems. It accounts for thermal coupling between multiple heat sources. Transient electro-thermal coupling can easily be taken into account by system designers. The method is based on a definition of the Optimal Thermal Coupling Point, which is proven to be valid even for transient modelling. Compared to the existing methods, the number of needed 3D thermal simulations or measurements is significantly reduced., Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions)
Published: 2007

31. Study of a Vertical Boiling Flow in Rectangular Mini-Channels

Author: Philippe Marty, Nadia Caney, Francesc Madrid, Freescale Semiconductor, Toulouse, Freescale semiconductor, Laboratoire des Écoulements Géophysiques et Industriels [Grenoble] (LEGI), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)
Subjects: Fluid Flow and Transfer Processes, Superficial velocity, Materials science, Critical heat flux, Mechanical Engineering, Thermodynamics, 02 engineering and technology, Heat transfer coefficient, Mechanics, Condensed Matter Physics, 01 natural sciences, 010305 fluids & plasmas, Physics::Fluid Dynamics, 020303 mechanical engineering & transports, 0203 mechanical engineering, Heat flux, Boiling, 0103 physical sciences, [PHYS.MECA.THER]Physics [physics]/Mechanics [physics]/Thermics [physics.class-ph], Flow coefficient, Two-phase flow, [PHYS.MECA.MEFL]Physics [physics]/Mechanics [physics]/Fluid mechanics [physics.class-ph], Nucleate boiling
Abstract: International audience; Mini-channel heat exchangers with boiling flows present optimal performances: they are highly efficient and compact and require low fluid mass. However, classical correlations for two-phase flow in macro-channels fail in predicting the heat transfer coefficient and the eventual premature dry-out in mini-channels. Therefore, new studies are needed to provide better knowledge on flow boiling phenomena in small, confined spaces. The proposed paper presents an experimental study of vertical flow boiling in mini-channels. The pressure drop and the heat transfer coefficient in the test section have been measured for a variety of conditions. Different heat flux, inlet vapor quality, and mass flow rate values have been tested. A critical dry-out vapor quality depending on the mass flow rate has been found. Nevertheless, the superficial velocity appears to be much more appropriate than the vapor quality or the mass flow rate for the dry-out occurrence prediction. A clean dependence with a single critical velocity value has been found.
Published: 2007
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32. Flow boiling study in mini-channels

Author: Nadia Caney, Francesc Madrid, Philippe-H. Marty, Freescale Semiconductor, Toulouse, Freescale semiconductor, Laboratoire des Écoulements Géophysiques et Industriels [Grenoble] (LEGI), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)
Subjects: Chemistry, Critical heat flux, Plate heat exchanger, Thermodynamics, 02 engineering and technology, Mechanics, Heat transfer coefficient, [SPI.MECA.MEFL]Engineering Sciences [physics]/Mechanics [physics.med-ph]/Fluids mechanics [physics.class-ph], Physics::Fluid Dynamics, 020303 mechanical engineering & transports, NTU method, 0203 mechanical engineering, 13. Climate action, Boiling, Micro heat exchanger, Flow coefficient, [PHYS.MECA.MEFL]Physics [physics]/Mechanics [physics]/Fluid mechanics [physics.class-ph], Nucleate boiling
Abstract: Mini-channel heat exchangers improve thermal performance in comparison to conventional macro-channel heat exchangers, being highly efficient, compact and requiring low fluid mass. However, classical correlations for two-phase flow in macro-channels fail in predicting the heat transfer coefficient in mini-channels. Therefore, new studies are needed in order to provide better knowledge on flow boiling phenomena in confined spaces. The proposed paper presents an experimental study on two-phase vertical flow boiling in mini-channels. The aim of this work is to determine the heat transfer coefficient and to study the pressure drop in a mini-channel heat exchanger (hydraulic diameter of 840μm) in order to obtain better understanding of the flow boiling mechanisms. A vertical upward flow test section is connected to a primary HFE-7100 circuit. A preheater imposes a given sub-cooled fluid temperature or a given two-phase vapour quality at the inlet. Downstream in the test loop, the fluid is condensed and pumped again into the test section. The pressure drop and the heat transfer coefficient in the test section have been measured for a variety of conditions. Different heat flux, inlet vapour quality and mass flow rate values have been tested. For the heat transfer coefficient, a correlating model is proposed as a function of the superficial velocity. This parameter appears to be much more appropriate than the vapour quality or the mass flow rate for dry-out occurrence prediction. A single critical velocity value has been found.Copyright © 2006 by ASME
Published: 2006
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33. Characterization of post-copper CMP surfaces with scanning probe microscopy Part 1: Surface leakage measurement with conductive atomic force microscopy

Author: Dominget, Alexandre, Farkas, J., Szunerits, Sabine, Freescale Semiconductor, Freescale semiconductor, Laboratoire d'Electrochimie et de Physico-chimie des Matériaux et des Interfaces (LEPMI ), and Institut de Chimie du CNRS (INC)-Institut National Polytechnique de Grenoble (INPG)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Joseph Fourier - Grenoble 1 (UJF)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)
Subjects: Atomic force microscopy (AFM), Surface leakage, Chemical mechanical polishing (CMP), [CHIM.MATE]Chemical Sciences/Material chemistry, Copper interconnects
Abstract: International audience; We demonstrate in this paper for the first time the use of conductive atomic force microscopy (AFM) to measure surface leakage between copper structures with varying line width and spacing in the micro and sub micrometer ranges. Conducting atomic force microscopy allows subsequent measurement of the topography as well as the electrical properties of surfaces. The feasibility and interest of these measurements will be shown by studying the impact of chemical mechanical polishing (CMP) of an electrical interface bearing different micrometric copper structures. As expected the polishing time has a crucial impact on the current determined between closely spaced copper structures. This paper will also deal with issues observed during the measurement.
Published: 2006
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34. Process window OPC verification: dry versus immersion lithography for the 65nm node

Author: Jerome Belledent, Patrick Schiavone, F. Foussadier, Christophe Couderc, Kevin Lucas, Frank Sundermann, Yorick Trouiller, Jean-Christophe Urbani, Amandine Borjon, Yves Rody, Christian Gardin, Laboratoire des technologies de la microélectronique (LTM), Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Philips France Semiconducteurs, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Freescale Semiconductor (FREESCALE SEMICONDUCTOR), Freescale semiconductor, STMicroelectronics [Crolles] (ST-CROLLES), Donis G. Flagello, Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS)
Subjects: Engineering, Proximity effect (electron beam lithography), Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, 010309 optics, Optics, Optical proximity correction, process window, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Miniaturization, failure prediction, Process window, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Lithography, Immersion lithography, business.industry, Process (computing), 021001 nanoscience & nanotechnology, ORC, resist modelling, Node (circuits), 0210 nano-technology, business, OPC
Abstract: Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. To verify the printability of a design across process window, compact optical models similar to those used for standard OPC are used. These models are calibrated from experimental data measured at the limits of the process window. They are then applied to the design to predict potential printing failures. This approach has been widely used for dry lithography. With the emergence of immersion lithography in production in the IC industry, the predictability of this approach has to be validated on this new lithographic process. In this paper, a comparison between the dry lithography process model and the immersion lithography process model is presented for the Poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two processes are compared with experimental results. A comparison in terms of process performance will also be a part of this study.
Published: 2006
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35. Critical failure ORC: Improving model accuracy through enhanced model generation

Author: Amandine Borjon, Patrick Schiavone, Frank Sundermann, Kyle Patterson, Yorick Trouiller, Jean-Christophe Urbani, Jerome Belledent, Kevin Lucas, Yves Rody, Christian Gardin, Christophe Couderc, Stanislas Baron, F. Foussadier, Laboratoire des technologies de la microélectronique (LTM), Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Philips France Semiconducteurs, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Freescale Semiconductor (FREESCALE SEMICONDUCTOR), Freescale semiconductor, STMicroelectronics [Crolles] (ST-CROLLES), Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS)
Subjects: Computer science, SVM, 020208 electrical & electronic engineering, Process (computing), Process window, 02 engineering and technology, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Support vector machine, Reduction (complexity), Optical proximity correction, ORC, Failure prediction, Statistical learning theory, 0202 electrical engineering, electronic engineering, information engineering, Node (circuits), Electrical and Electronic Engineering, 0210 nano-technology, Algorithm, OPC, Aerial image
Abstract: Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification methods have become indispensable tools for avoiding pattern printing issues. A post-OPC verification technique known as critical failure optical rule checking (CFORC) was recently introduced and has proven its efficiency for detecting potential printing issues through the entire process window [S.D. Shang et al., Proc. SPIE 5040 (2003); J. Belledent et al., Proc. SPIE 5377 (2004); A. previous termBorjonnext term et al., Proc. SPIE 5754 (2005)]. This methodology uses optical parameters from aerial image simulations at single process condition. A numerical model, build using support vector machine (SVM) principle [The Nature of Statistical Learning Theory, second ed., Springer, (1995)], correlates these optical parameters with experimental data taken throughout the process window to predict printing failures. This statistical method however leads to some false predictions. Although false predictions may be unavoidable in statistical methodologies, it is possible to lower their rate of occurrence. In this study, concentrated on contact layer patterning for the 90 nm node and the poly layer patterning for the 65 nm node, the accuracy of CFORC models is improved through several approaches: enhancing the normalization algorithm, optimization of fitting parameters and optimizing the parameter space coverage.
Published: 2006
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36. Characterization of post-copper CMP surface with scanning probe microscopy: Part II: Surface potential measurements with scanning Kelvin probe force microscopy

Author: J. Farkas, Sabine Szunerits, A. Dominget, Freescale Semiconductor, Freescale semiconductor, Laboratoire d'Electrochimie et de Physico-chimie des Matériaux et des Interfaces (LEPMI ), and Institut de Chimie du CNRS (INC)-Institut National Polytechnique de Grenoble (INPG)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Joseph Fourier - Grenoble 1 (UJF)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)
Subjects: Analytical chemistry, chemistry.chemical_element, 02 engineering and technology, Scanning capacitance microscopy, 01 natural sciences, chemical mechanical polishing (CMP), Scanning probe microscopy, 0103 physical sciences, Microscopy, Electrical and Electronic Engineering, 010302 applied physics, Kelvin probe force microscope, atomic force microscopy, business.industry, Conductive atomic force microscopy, [CHIM.MATE]Chemical Sciences/Material chemistry, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Copper, post-CMP cleaning, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, chemistry, Scanning ion-conductance microscopy, Optoelectronics, 0210 nano-technology, business, Non-contact atomic force microscopy
Abstract: International audience; We demonstrate in this paper for the first time the use of Scanning Kelvin Probe Force Microscopy (KFM) to characterize post-CMP copper structures with varying line width and spacing. This work is in the continuity of previously published results concerning surface leakage measurements with conductive Atomic Force Microscopy. The feasibility of KFM will be shown by studying patterned samples and post-CMP copper samples. Results show clearly the capability of this technique in the detection of metallic contamination. It has also been observed that a post-CMP cleaning solution impacts the copper work function. A special study has been done by varying the pH of a cleaning solution. Moreover, electrostatic simulations have been performed to analyse the results obtained for patterned wafers.
Published: 2006
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37. New lateral DMOS and IGBT structures realized on a partial SOI substrate based on LEGO process

Author: Marise Bafleur, R. Ng, B. Rousset, I. Bertrand, E. Imbernon, J.M. Dilhac, H. Granier, V. Pathirana, Florin Udrea, Freescale Semiconducteurs, University of Cambridge [UK] (CAM), Service Techniques et Équipements Appliqués à la Microélectronique (LAAS-TEAM), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire commun LCIP2 avec Freescale Semiconductor, Freescale Semiconductor, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées
Subjects: 010302 applied physics, LDMOS, Materials science, business.industry, Electrical engineering, Silicon on insulator, Recrystallization (metallurgy), High voltage, 02 engineering and technology, Insulated-gate bipolar transistor, 021001 nanoscience & nanotechnology, LIGBT, 01 natural sciences, 7. Clean energy, Current injection technique, 0103 physical sciences, MOSFET, Optoelectronics, Power semiconductor device, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Partial SOI, LEGO
Abstract: International audience; In this paper, we present new lateral DMOS and IGBT structures based on a partial SOI substrate. The partial SOI substrate, formed through LEGO recrystallization process improves considerably the breakdown capability and the thermal behavior of these devices compared to full SOI devices. Experimental results of high voltage power devices implemented on such a process are presented for the first time.
Published: 2005

38. Ultra-thin strained SOI substrate analysis by pseudo-MOS measurements

Author: E. Latu-Romain, Thomas Ernst, Sorin Cristoloveanu, Ian Cayrefourcq, D. Delille, N. Bresson, C. Gallon, F. Fournel, S. Bord, Thomas Skotnicki, B. Ghyselen, Francois Andrieu, J.M. Hartmann, Cecile Aulnette, Yves Campidelli, Frederic Allibert, Claire Fenouillet-Beranger, N. Kernevez, STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique (IMEP), Université Joseph Fourier - Grenoble 1 (UJF)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), SOITEC, Philips France Semiconducteurs, Freescale Semiconductor, Freescale semiconductor, Laboratoire d'Electrochimie et de Physico-chimie des Matériaux et des Interfaces (LEPMI ), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Institut de Chimie du CNRS (INC)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF), and Institut de Chimie du CNRS (INC)-Institut National Polytechnique de Grenoble (INPG)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Joseph Fourier - Grenoble 1 (UJF)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)
Subjects: Materials science, Silicon, ultra-thin strained SOI, 020209 energy, chemistry.chemical_element, Silicon on insulator, 02 engineering and technology, 01 natural sciences, Soi substrate, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Wafer, Electrical and Electronic Engineering, 010302 applied physics, pseudo-MOS measurements, business.industry, Relaxation (NMR), [CHIM.MATE]Chemical Sciences/Material chemistry, Condensed Matter Physics, Thermal conduction, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, chemistry, Optoelectronics, business, Voltage
Abstract: International audience; Pseudo-MOS (Ψ -MOSFET) measurements are a simple and rapid technique for an accurate evaluation of SOI wafer intrinsic electrical properties, prior to any CMOS processing. For the first time, we report Ψ -MOSFET measurements performed on Strained SOI (SSOI) wafers with ultra-thin silicon films (9.5 nm to 17.5 nm). To take into account the wafer specificities and the use of such thin conduction layers, adapted Ψ -MOSFET models and parameter extraction methods were necessary. The experiments show an increase of the threshold and flat band voltages and a mobility reduction as the strained film becomes thinner. Further electrical analyses, coupled with several morphological studies, do not reveal any relaxation of the strain in the thinnest films. The mobility is clearly enhanced in SSOI as compared with standard SOI substrates.
Published: 2005
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39. Hybrid BIST Based on Repeating Sequences and Cluster Analysis

Author: Lei Li, Krishnendu Chakrabarty, Freescale Semiconductor, Inc., Austin, Freescale Semiconductor, Inc., Austin TX, EE Dept., Duke University [Durham]-Freescale Semiconductor, Inc., Austin TX, EDAA - European design and Automation Association, and Publishing Association, EDA
Subjects: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Engineering, Real-time computing, Test compression, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 010501 environmental sciences, ENCODE, 01 natural sciences, Fault detection and isolation, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, 0105 earth and related environmental sciences, Sequence, Basis (linear algebra), business.industry, Pattern recognition, [SPI.TRON] Engineering Sciences [physics]/Electronics, 020202 computer hardware & architecture, [SPI.TRON]Engineering Sciences [physics]/Electronics, Built-in self-test, Benchmark (computing), Artificial intelligence, business, Test data
Abstract: Submitted on behalf of EDAA (http://www.edaa.com/); International audience; We present a hybrid BIST approach that extracts the most frequently occurring sequences from deterministic test patterns; these extracted sequences are stored on-chip. We use cluster analysis for sequence extraction, and encode deterministic patterns on the basis of the stored sequences. Experimental results for the ISCAS-89 benchmark circuits show that the proposed approach often requires less on-chip storage and test data volume than other recent BIST methods.
Published: 2005

40. Through-process window resist modelling strategies for the 65 nm node

Author: Borjon, Amandine, Belledent, Jerôme, Trouiller, Yorick, Patterson, Kyle, Lucas, Kevin, Couderc, Christophe, Sundermann, Frank, Urbani, Jean-Christophe, Baron, Stanislas, Rody, Yves, Gardin, Christian, Foussadier, Frank, Schiavone, Patrick, Laboratoire des technologies de la microélectronique (LTM), Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Philips France Semiconducteurs, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Freescale Semiconductor (FREESCALE SEMICONDUCTOR), Freescale semiconductor, STMicroelectronics [Crolles] (ST-CROLLES), J. Tracy Weed, Patrick M. Martin, Schiavone, Patrick, Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS), and Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)
Abstract: Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification methods have become indispensable tools for avoiding pattern printing issues. The majority of these methods are primarily based on lithographic simulations of pattern printing behaviour across dose and focus variations. The models used for these simulations are compact optical models combined with one single resist model. Even if very predictive resist models exist, they have often a large number of parameters to fit and suffer from long computing times to execute the simulations. Simplified resist models are thus needed to enhance run-time computing during simulation. The objective of this study is to test the predictability of such resist models across the process window. Two different resist models will be considered in this study. The first resist model is a pure variable threshold resist model. The second resist modelling approach is a simplified physical model which uses Gaussian convolutions and a constant threshold to model resist printing behaviour. The study concentrates on poly layer patterning for the 65 nm node. Examples of specific simulations obtained with the two different techniques are compared against experimental results.
Published: 2005

41. Printability of nonsmoothed buried defects in extreme ultraviolet lithography mask blanks

Author: Marieke Richard, Rafik Smaali, Vincent Farys, Patrick Schiavone, Etienne Quesnel, Viviane Muffato, Patrick P. Naulleau, Jean-Yves Robic, Sergei V. Postnikov, M. Besacier, Christelle Charpin-Nicolle, STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire des technologies de la microélectronique (LTM), Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Freescale Semiconductor (FREESCALE SEMICONDUCTOR), Freescale Semiconductor Inc., Center for X-Ray Optics [LBNL Berkeley] (CXRO), Lawrence Berkeley National Laboratory [Berkeley] (LBNL), Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS)
Subjects: 010302 applied physics, Masking (art), defect, Materials science, business.industry, Texture (cosmology), Extreme ultraviolet lithography, General Engineering, 01 natural sciences, Blank, 010309 optics, Optics, Stack (abstract data type), Sputtering, Extreme ultraviolet, 0103 physical sciences, Optoelectronics, lithography, EUV, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Lithography, 85.40.Hp
Abstract: One of the most important challenges in extreme ultraviolet lithography is the need to provide mask blanks free of defects. In order to provide experimental results on the printability of buried defects, a dedicated extreme ultraviolet (EUV) mask blank was manufactured using ion beam sputtering (IBS) with a nonsmoothing process. Using this kind of process, the effect of the buried defect is apparent throughout the entire multilayer stack. The disturbance generated in the multilayer, measured using an atomic force microscope (AFM), shows lateral growth and a slight vertical smoothing effect. Here we report the printability results obtained with this kind of defect. One result concerns the influence of the defect density on the printability. We show that the major effect can be attributed to local flare, which depends on the pattern density. In order to better understand the printability mechanism of this kind of buried defect, we also compared the experimental results with electromagnetic simulation.
Published: 2005
Full Text: View/download PDF

42. Printability of nonsmoothed buried defects in extreme ultraviolet lithography mask blank

Author: Farys, V., Charpin, C., Richard, Murielle, Robic, J.Y, Muffato, V., Quesnel, E., Postnikov, S., Schiavone, Patrick, Besacier, M., Smaali, Rafik, Naulleau, P., Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Freescale Semiconductor (FREESCALE SEMICONDUCTOR), Freescale Semiconductor Inc., Laboratoire des technologies de la microélectronique (LTM), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS), Georgia Tech Lorraine [Metz], Université de Franche-Comté (UFC), and Université Bourgogne Franche-Comté [COMUE] (UBFC)-Université Bourgogne Franche-Comté [COMUE] (UBFC)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Georgia Institute of Technology [Atlanta]-CentraleSupélec-Ecole Nationale Supérieure des Arts et Metiers Metz-Centre National de la Recherche Scientifique (CNRS)
Subjects: ComputingMilieux_MISCELLANEOUS
Abstract: International audience
Published: 2005

43. High Accuracy 65nm OPC Verification: Full Process Window Model vs. Critical Failure ORC

Author: Frank Sundermann, Olivier Toublan, Amandine Borjon, Yorick Trouiller, Patrick Schiavone, Shumay D. Shang, Jean-Christophe Urbani, Yves Rody, Christophe Couderc, Kyle Patterson, Corinne Miramond, Jerome Belledent, Kevin Lucas, Stanislas Baron, Laboratoire des technologies de la microélectronique (LTM), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS), Philips France Semiconducteurs, Mentor Graphics Corp. (MENTOR GRAPHICS), Mentor Graphics, Mentor Graphics Europe (MENTOR GRAPHICS), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), Freescale Semiconductor (FREESCALE SEMICONDUCTOR), Freescale semiconductor, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Bruce W. Smith, and Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)
Subjects: 010302 applied physics, Engineering, business.industry, Process (computing), Experimental data, 02 engineering and technology, 01 natural sciences, Reduction (complexity), 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Range (statistics), 020201 artificial intelligence & image processing, Node (circuits), Process window, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Lithography, Algorithm, Simulation, Aerial image
Abstract: It is becoming more and more difficult to ensure robust patterning after OPC due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. The techniques of Mask Rule Checking (MRC) and Optical Rule Checking (ORC) have become mandatory tools for ensuring that OPC delivers robust patterning. However the first method relies on geometrical checks and the second one is based on a model built at best process conditions. Thus those techniques do not have the ability to address all potential printing errors throughout the process window (PW). To address this issue, a technique known as Critical Failure ORC (CFORC) was introduced that uses optical parameters from aerial image simulations. In CFORC, a numerical model is used to correlate these optical parameters with experimental data taken throughout the process window to predict printing errors. This method has proven its efficiency for detecting potential printing issues through the entire process window [1]. However this analytical method is based on optical parameters extracted via an optical model built at single process conditions. It is reasonable to expect that a verification method involving optical models built from several points throughout PW would provide more accurate predictions of printing errors for complex features. To verify this approach, compact optical models similar to those used for standard OPC were built and calibrated with experimental data measured at the PW limits. This model is then applied to various test patterns to predict potential printing errors. In this paper, a comparison between these two approaches is presented for the poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two techniques are compared with experimental results. The details of implementing these two techniques on full product layouts are also included in this study.
Published: 2005

44. Tone detector and method therefor

Author: Pessoa, Lucio F. C., Valentin Emiya, David Melles, Delphine Vallot, FreeScale Semiconductor Inc., Freescale Semiconductor Inc., and Emiya, Valentin
Subjects: [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [INFO.INFO-NI] Computer Science [cs]/Networking and Internet Architecture [cs.NI], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-TS] Computer Science [cs]/Signal and Image Processing, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing
Published: 2002

45. Origin of reverse annealing effect in hydrogen-implanted silicon

Author: Theodore, N [Silicon Technology Solutions, Freescale Semiconductor Inc., Tempe, Arizona 85284 (United States)]
Published: 2010
Full Text: View/download PDF

46. Dopant activation in ion implanted silicon by microwave annealing

Author: Theodore, N [Silicon Technology Solutions, Freescale Semiconductor Inc., 2100 East Elliot Rd., Tempe, Arizona 85284 (United States)]
Published: 2009
Full Text: View/download PDF

47. Evolution of implantation induced damage under further ion irradiation: Influence of damage type

Author: Theodore, N [Silicon Technology Solutions, Freescale Semiconductor Inc., Tempe, Arizona 85284 (United States)]
Published: 2009
Full Text: View/download PDF

48. Evidence for ion irradiation induced dissociation and reconstruction of Si-H bonds in hydrogen-implanted silicon

Author: Theodore, N [Analog and Mixed-Signal Technologies, Freescale Semiconductor Inc., Tempe, Arizona 85284 (United States)]
Published: 2008
Full Text: View/download PDF

49. Effects of hydrogen implantation temperature on InP surface blistering

Author: Theodore, N [Analog and Mixed-Signal Technologies, Freescale Semiconductor Inc., Tempe, Arizona 85284 (United States)]
Published: 2008
Full Text: View/download PDF

50. Cracking in hydrogen ion-implanted Si/Si{sub 0.8}Ge{sub 0.2}/Si heterostructures

Author: Theodore, N [Analog and Mixed-Signal Technologies, Freescale Semiconductor, Inc., Tempe, Arizona 85284 (United States)]
Published: 2008
Full Text: View/download PDF

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