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Critical failure ORC: Improving model accuracy through enhanced model generation

Authors :
Amandine Borjon
Patrick Schiavone
Frank Sundermann
Kyle Patterson
Yorick Trouiller
Jean-Christophe Urbani
Jerome Belledent
Kevin Lucas
Yves Rody
Christian Gardin
Christophe Couderc
Stanislas Baron
F. Foussadier
Laboratoire des technologies de la microélectronique (LTM)
Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)
Philips France Semiconducteurs
Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI)
Direction de Recherche Technologique (CEA) (DRT (CEA))
Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)
Freescale Semiconductor (FREESCALE SEMICONDUCTOR)
Freescale semiconductor
STMicroelectronics [Crolles] (ST-CROLLES)
Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)
Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS)
Source :
Microelectronic Engineering, Microelectronic Engineering, Elsevier, 2006, 83, Issues 4-9, pp.1017-1022. ⟨10.1016/j.mee.2006.01.034⟩, Microelectronic Engineering, 2006, 83, Issues 4-9, pp.1017-1022. ⟨10.1016/j.mee.2006.01.034⟩
Publication Year :
2006
Publisher :
HAL CCSD, 2006.

Abstract

Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification methods have become indispensable tools for avoiding pattern printing issues. A post-OPC verification technique known as critical failure optical rule checking (CFORC) was recently introduced and has proven its efficiency for detecting potential printing issues through the entire process window [S.D. Shang et al., Proc. SPIE 5040 (2003); J. Belledent et al., Proc. SPIE 5377 (2004); A. previous termBorjonnext term et al., Proc. SPIE 5754 (2005)]. This methodology uses optical parameters from aerial image simulations at single process condition. A numerical model, build using support vector machine (SVM) principle [The Nature of Statistical Learning Theory, second ed., Springer, (1995)], correlates these optical parameters with experimental data taken throughout the process window to predict printing failures. This statistical method however leads to some false predictions. Although false predictions may be unavoidable in statistical methodologies, it is possible to lower their rate of occurrence. In this study, concentrated on contact layer patterning for the 90 nm node and the poly layer patterning for the 65 nm node, the accuracy of CFORC models is improved through several approaches: enhancing the normalization algorithm, optimization of fitting parameters and optimizing the parameter space coverage.

Details

Language :
English
ISSN :
01679317 and 18735568
Database :
OpenAIRE
Journal :
Microelectronic Engineering, Microelectronic Engineering, Elsevier, 2006, 83, Issues 4-9, pp.1017-1022. ⟨10.1016/j.mee.2006.01.034⟩, Microelectronic Engineering, 2006, 83, Issues 4-9, pp.1017-1022. ⟨10.1016/j.mee.2006.01.034⟩
Accession number :
edsair.doi.dedup.....dfb2f29442c8d94a5b03357359bfa6ef
Full Text :
https://doi.org/10.1016/j.mee.2006.01.034⟩