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We present a physics-based circuit-compatible model for pH-sensitive field-effect transistors based on 2-D materials. The electrostatics along the electrolyte-gated 2-D-semiconductor stack is treated by solving the Poisson equation, including the site-binding model and the Gouy–Chapman–Stern approach, while the carrier transport is described by the drift-diffusion theory. The proposed model is provided in an analytical form and then implemented in Verilog-A, making it compatible with standard technology computer-aided design tools employed for circuit simulation. The model is benchmarked against two experimental transition-metal-dichalcogenide (MoS2 and ReS2)-based ion sensors, showing excellent agreement when predicting the drain current, threshold voltage shift, and current/voltage sensitivity measurements for different pH concentrations.

In this work, a physics-based unified compact model for III-V GAA FET electrostatics is proposed. The model considers arbitrary cross-sectional geometry of GAA FETs viz. rectangular, circular and elliptical. A comprehensive model for cuboid GAA FETs is developed first using the constant charge density approximation. The model is then combined with the earlier developed model for cylindrical GAA FETs to have a unified representation. The efficacy of the model is validated by comparing it with simulation data from a 2D coupled Poisson-Schrodinger solver. The proposed model is found to be, (a) accurate for GAA FETs with different geometries, dimensions and channel materials and (b) computationally efficient.

The combination of graphene and silicon in hybrid electronic devices has attracted increasing attention over the last decade. Here, a unique technology of graphene-on-silicon heterostructures as solution-gated transistors for bioelectronics applications is presented. The proposed graphene-onsilicon field-effect transistors (GoSFETs) are fabricated by exploiting various conformations of channel doping and dimensions. The fabricated devices demonstrate hybrid behavior with features specific to both graphene and silicon, which are rationalized via a comprehensive physics-based compact model which is purposely implemented and validated against measured data. The developed theory corroborates that the device hybrid behavior can be explained in terms of two independent silicon and graphene carrier transport channels, which are, however, strongly electrostatically coupled. Although GoSFET transconductance and carrier mobility are found to be lower than in conventional silicon or graphene field-effect transistors, it is observed that the combination of both materials within the hybrid channel contributes uniquely to the electrical response. Specifically, it is found that the graphene sheet acts as a shield for the silicon channel, giving rise to a nonuniform potential distribution along it, which impacts the transport, especially at the subthreshold region, due to non-negligible diffusion current., MCIN/AEI PID2020-116518GB-I00, FEDER/Junta de Andalucia-Consejeria de Transformacion Economica, Industria, Conocimiento y Universidades A-TIC-646-UGR20 B-RNM-375-UGR18 PY20_00633, European Commission 825213, PAIDI 2020, European Social Fund Operational Programme 2014-2020 20804, MCIN/AEI/PTA grant PTA2020-018250-I, Projekt DEAL

We thoroughly compare the DC electrical behavior of n-MOS transistors based on Si nanowires with 〈 1 0 0 〉 and 〈 1 1 0 〉 channel orientations by means of Multi-Subband Ensemble Monte Carlo simulations. We find that the drain current depends on the nanowire diameter and it is slightly, but consistently, larger for 〈 1 0 0 〉 than for 〈 1 1 0 〉 nanowires. The observed differences in mobility, velocity and spatial charge distribution are interpreted in terms of the effective masses and populations of the different Si conduction band valleys, whose sixfold degeneracy is lifted by quantum confinement in narrow nanowires. Finally, we study the scaling behavior for channel lengths down to 8 nm, concluding that the differences observed between orientations are minimal.

The III–V materials have a highly non-parabolic band structure that significantly affects the MOS transistor electrostatics. The compact models used to simulate circuits involving III–V MOS transistors must account for this band structure non-parabolicity for accurate results. In this work, we propose a modification to the energy dispersion relation to include the band structure non-parabolicity in a way suitable for compact models. Unlike the available non-parabolic energy dispersion relation, the one proposed here is simple and includes the non-parabolicity in both confinement and transport directions. The proposed dispersion relation is then used to model the electrostatics of III–V nanowire transistors. The proposed model is scalable to a higher number of sub-bands and computationally efficient for circuit simulators. The model is also validated with the data from a 2D Poisson–Schrodinger solver for a wide range of nanowire dimensions, III–V channel materials, and found to be in excellent agreement with the simulation data.

BioFETs based on two-dimensional materials (2DMs) offer a unique opportunity to enhance, at a low cost, the sensitivity of current biosensors enabling the design of compact devices compatible with standard CMOS technology. The unique combination of large exposed surface areas and minimal thicknesses of 2DMs is an outstanding feature for these devices, and the assessment of their behaviour requires combined experimental and theoretical efforts. In this work we present a 2D-material based BioFET simulator including complex electrolyte reactions and analysing different models for the electrolyte-molecule interaction. These models describe how the molecular charge is screened by the electrolyte ions when their distributions are modified. The electrolyte simulation is validated against experimental results as well as against the analytical predictions of the Debye-Hückel approximation. The role of the electrolyte charge screening as well as the impact of the interaction model on the device responsivity are analysed in detail. The results are discussed in order to conclude about the consequences of employing different interaction approximations for the simulation of BioFETs and more generally on the correct modelling of biomolecule-device interaction in BioFETs.

Considering the demand of III–V multigate (MUG) transistors for next-generation CMOS technologies, a compact model is required to test their performance in different circuits. The low effective mass and highly confined geometry of these MUG devices demand the use of computationally expensive coupled Poisson–Schrodinger (PS) solver for terminal charges and surface potential. In this paper, we propose an approximation, which decouples the PS equations and enables the development of a computationally efficient analytical model. The surface potential and semiconductor charge equations for III–V low effective mass channel cylindrical nanowire (NW) transistors are derived using the proposed approximation. The proposed model is physics-based and does not include any empirical parameters. The accuracy of the model is verified across NWs of different sizes and materials using the data from the 2-D PS solver and found to be accurate.

We present a graphene-based phase shifter for radio-frequency (RF) phase-array applications. The core of the designed phase-shifting system consists of a graphene field-effect transistor (GFET) used in a common source amplifier configuration. The phase of the RF signal is controlled by exploiting the quantum capacitance of graphene and its dependence on the terminal transistor biases. In particular, by independently tuning the applied gate-to-source and drain-to-source biases, we observe that the phase of the signal, in the super-high frequency band, can be varied nearly 200 degrees with a constant gain of 2.5 dB. Additionally, if only the gate bias is used as control signal, and the drain is biased linearly dependent on the former (i.e., in a completely analogue operation), a phase shift of 85 degrees can be achieved making use of just one transistor and keeping a gain of 0 dB with a maximum variation of 1.3 dB. The latter design can be improved by applying a balanced branch-line configuration showing to be competitive against other state-of-the-art phase shifters. This work paves the way towards the exploitation of graphene technology to become the core of active analogue phase shifters for high-frequency operation., Comment: 10 pages, 10 figures, 2 tables

A. Toral-Lopez acknowledges the FPU program (FPU16/04043). E. G. Marin acknowledges Juan de la Cierva Incorporación IJCI-2017-32297 (MINECO/AEI). This work has received funding from the European Unions Horizon 2020 Research and Innovation Programme under grant agreements No. GrapheneCore2 785219 and No. GrapheneCore3 881603, and from Ministerio de Ciencia, Innovación y Universidades under grant agreement RTI2018-097876-B-C21 (MCIU/AEI/FEDER, UE), TEC2017- 89955-P (MINECO/AEI/FEDER, UE), and TEC2015-67462-C2-1- R (MINECO). This article has been partially funded by the European Regional Development Funds (ERDF) allocated to the Programa Operatiu FEDER de Catalunya 2014–2020, with support of the Secretaria d’Universitats i Recerca of the Departament d’Empresa i Coneixement of the Generalitat de Catalunya for Emerging Technology Clusters to carry out valorization and transfer of research results. GraphCAT project 001-P-001702., Two-dimensional materials (2DMs) are a promising alternative to complement and upgrade high-frequency electronics. However, in order to boost their adoption, the availability of numerical tools and physically-based models able to support the experimental activities and to provide them with useful guidelines becomes essential. In this context, we propose a theoretical approach that combines numerical simulations and small-signal modeling to analyze 2DM-based FETs for radio-frequency applications. This multi-scale scheme takes into account non-idealities, such as interface traps, carrier velocity saturation, or short channel effects, by means of self-consistent physics-based numerical calculations that later feed the circuit level via a small-signal model based on the dynamic intrinsic capacitances of the device. At the circuit stage, the possibilities range from the evaluation of the performance of a single device to the design of complex circuits combining multiple transistors. In this work, we validate our scheme against experimental results and exemplify its use and capability assessing the impact of the channel scaling on the performance of MoS2-based FETs targeting RF applications., FPU program (FPU16/04043), Juan de la Cierva Incorporación IJCI-2017-32297 (MINECO/AEI), European Unions Horizon 2020 Research and Innovation Programme under grant agreements No. GrapheneCore2 785219 and No. GrapheneCore3 881603, Ministerio de Ciencia, Innovación y Universidades under grant agreement RTI2018-097876-B-C21 (MCIU/AEI/FEDER, UE), TEC2017- 89955-P (MINECO/AEI/FEDER, UE), and TEC2015-67462-C2-1- R (MINECO), European Regional Development Funds (ERDF) allocated to the Programa Operatiu FEDER de Catalunya 2014–2020, with support of the Secretaria d’Universitats i Recerca of the Departament d’Empresa i Coneixement of the Generalitat de Catalunya for Emerging Technology Clusters, GraphCAT project 001-P-001702

Small $\Gamma-L$ valley energy offset in III-V materials such as GaAs is shown to improve the transistor performance, overcoming the density of states bottleneck while maintaining high injection velocity. Existing compact models for III-V channel transistors only account for the dominant $\Gamma$ -valley charges. This underestimates the transistors circuit performance. In this work, for the first time, a compact model is introduced to include the $L$ -valley charges in III-V GAA transistor electrostatics. The quantum mechanical effects arising because of the highly confined GAA geometry is also included. The proposed model is compared with the data obtained from 2D Poisson-Schrodinger solver for different III-V channel materials and dimensions and found to be in excellent agreement.

In this paper, we present a channel thickness dependent analytical model for MoS 2 symmetric double-gate FETs aiming at circuit simulation. To validate the model behavior, density functional theory (DFT) calculations are taken into account to obtain numerical data of N-layer ( $\mathbf{N}=\mathbf{1,2,3,4}$ , and 5) MoS 2 accounting for the $K$ and $\Lambda$ valley dependent effective masses and difference in energy levels. These extracted layer dependent material parameters are used as an input with layer independent mobility in DD simulator (coupled drift-diffusion and Poisson solver). The model shows excellent match for surface potential and drain current. The model prediction of digital figure of merits is also shown against the simulation data.

The search and investigation of resistive switching materials, the most consolidated form of solid-state memristors, has become one of the fastest growing areas in the field of electronics. This is not only due to the huge commercial interest in developing the so-called Resistive Random-Access Memories (ReRAMs) but also because resistive switching materials are gathering way to new forms of analog computation. Unlike in the field of traditional electronics technologies, where Silicon has monopolized most of the applications, the area of solid-state memristors is opened to a broad set of candidates that may contribute to unprecedented applications. In particular, the use of organic-based resistive switching materials can provide additional functionalities as structural flexibility for conformal integration or introduce new and cost-effective fabrication technologies. Following this new wave of organic memristive materials, this work aims at reviewing the existing models explaining the origins of resistive switching in Graphene Oxide, one of the most promising contenders on the battlefield of emerging memristive materials due to its low cost and easy processing methods. Within this manuscript, we will revisit the different theories supporting the phenomenology of resistive switching in this material nourishing the discussion with experimental results supporting the three main existing theories.

—In this paper, we present a channel thickness dependent analytical model for MoS2 symmetric double-gate FETs including negative capacitance (NC) effect. In the model development, first thickness dependent model of the baseline 2D FET is developed, and later NC effect is included in the model using the Landau-Khalatnikov (L-K) relation. To validate baseline model behavior, density functional theory (DFT) calculations are taken into account to obtain numerical data for the K and valley dependent effective masses and differences in the energy levels of N-layer (N = 1, 2, 3, 4, and 5) MoS2. The calculated layer dependent parameters using DFT theory are further used in a drift-diffusion simulator to obtain electric characteristics of the baseline 2D FET for model validation. The model shows excellent match for drain current and total gate capacitance of baseline FET and NCFET against the numerical simulation. Index Terms—Metal-oxide-semiconductor field-effect transistor (MOSFET), Compact modeling, molybdenum disulfide (MoS2), transition metal dichalcogenide (TMD), Double Gate (DG), Negative Capacitance FET (NCFET)., Swarnajayanti Fellowship, FIST Scheme of Department of Science and Technology (DST), Government of India, Spanish Government Grant FPU16/04043, Juan de la Cierva Incorporación (MINECO/AEI) IJCI-2017-32297

We developed a Multi-Subband Ensemble Monte Carlo simulator for non-planar devices, taking into account two-dimensional quantum confinement. It couples self-consistently the solution of the 3D Poisson equation, the 2D Schrödinger equation, and the 1D Boltzmann transport equation with the Ensemble Monte Carlo method. This simulator was employed to study MOS devices based on ultra-scaled Gate-All-Around Si nanowires with diameters in the range from 4 nm to 8 nm with gate length from 8 nm to 14 nm. We studied the output and transfer characteristics, interpreting the behavior in the sub-threshold region and in the ON state in terms of the spatial charge distribution and the mobility computed with the same simulator. We analyzed the results, highlighting the contribution of different valleys and subbands and the effect of the gate bias on the energy and velocity profiles. Finally the scaling behavior was studied, showing that only the devices with D = 4 nm maintain a good control of the short channel effects down to the gate length of 8 nm .

In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III–V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering the wave function penetration into the gate insulator, effective mass discontinuity at the semiconductor–oxide interface, 2-D confinement in the NW, and Fermi–Dirac statistics. The semiconductor charge expression proposed in this paper is completely explicit in terms of applied gate voltage, therefore, making it highly suitable for large circuit simulations. The model is also compared with the results from self-consistent Schrodinger–Poisson solver for different NW sizes and materials and found to be accurate over a wide range of gate voltages.

The Dirac voltage of a graphene field-effect transistor (GFET) stands for the gate bias that sets the charge neutrality condition in the channel, thus resulting in a minimum conductivity. Controlling its dependence on the terminal biases is crucial for the design and optimization of radio-frequency applications based on multiple GFETs. However, the previous analysis of such dependence carried out for a single device can lead to confusion and if not properly understood could result in circuit designs with poor performance. The control of the Dirac point shift (DPS) is particularly important for the deployment of graphene-based differential circuit topologies where keeping a strict symmetry between the electrical balanced branches is crucial for exploiting the advantages of such topologies. This note sheds light on the impact of terminal biases on the DPS in a real device and sets a rigorous methodology to control it so to eventually optimize and exploit the performance of radio-frequency applications based on GFETs., 7 pages, 3 figures, 1 table

This work investigates the sources of resistive switching (RS) in recently reported laser-fabricated graphene oxide memristors by means of two numerical analysis tools linked to the Time Series Statistical Analysis and the use of the Quantum Point Contact Conduction model. The application of both numerical procedures points to the existence of a filament connecting the electrodes that may be interrupted at a precise point within the conductive path, resulting in resistive switching phenomena. These results support the existing model attributing the memristance of laser-fabricated graphene oxide memristors to the modification of a conductive path stoichiometry inside the graphene oxide., The authors thank the support of the Spanish Ministry of Science, Innovation and Universities under projects TEC2017-89955-P, TEC2017-84321-C4-3-R, MTM2017-88708-P and project PGC2018-098860-B-I00 (MCIU/AEI/FEDER, UE), and the predoctoral grant FPU16/01451.

The optical properties of transparent conductive electrodes (TCEs) based on indium tin oxide (ITO) films deposited on polyethylene terephthalate (PET) substrates were evaluated in this work making use of the Inverse Adding-Doubling (IAD) iterative method. This technique allowed us to obtain the scattering and absorption coefficients explaining the optical behavior of the ITO-PET samples. The results pointed out that absorption is the most noticeable optical extinction process that occurs when light travels through this material.

The necessity of overcoming the limitations (e.g. weight, cost and brittleness) of traditional bulk semiconductors employed to build conventional photodetectors, has fueled the interest of the scientific community towards two-dimensional crystals. Its most representative member, graphene [1], with outstanding electrical and mechanical properties, has however a severely limited photoresponsivity due to 1) the lack of bandgap and 2) a reduced carrier lifetime that hardly reaches a few picoseconds [2]. Greater expectations lay on Transition Metal Dichalcogenides (TMDs) [3], the bandgap of which is sensitive to the number of layers. Moreover, TMDs can be stacked forming vertical or lateral heterojunctions [4] giving rise to structures similar to field-effect transistors (FETs) that behave as photodetectors. In this work we theoretically study the optoelectronic properties of a backgated phototransistor, with its channel formed by few-layer MoTe 2 , and we focus on the role played by the charges trapped at the channel-insulator interface through the photogating effect [5, 6].

In this work, we propose a physics-based compact model for square geometry gate-all-around quadruple-gate FET (QGFET) structure with a III-V semiconductor channel. The Poisson and the Schrodinger equations are decoupled using an energy perturbation approach. Using the recently proposed constant charge density approximation the potential inside the channel is modeled in a mathematically simple form. Using the approximation further the perturbation term is derived analytically. The model also takes into account the non-iso-potential insulator-semiconductor interface in QGFET. The proposed model is mathematically simple and computationally efficient for implementation in a circuit simulator. The model is validated against the data from a 2D Poisson-Schrodinger solver for QGFETs of different dimension and channel material.

Graphene / silicon (G/Si) heterostructures have been studied extensively in the past years for applications such as photodiodes, photodetectors and solar cells, with a growing focus on efficiency and performance. Here, a specific contact pattern scheme with interdigitated Schottky and graphene/insulator/silicon (GIS) structures is explored to experimentally demonstrate highly sensitive G/Si photodiodes. With the proposed design, an external quantum efficiency (EQE) of > 80 % is achieved for wavelengths ranging from 380 to 930 nm. A maximum EQE of 98% is observed at 850 nm, where the responsivity peaks to 635 mA/W, surpassing conventional Si p-n photodiodes. This efficiency is attributed to the highly effective collection of charge carriers photogenerated in Si under the GIS parts of the diodes. The experimental data is supported by numerical simulations of the diodes. Based on these results, a definition for the true active area in G/Si photodiodes is proposed, which may serve towards standardization of G/Si based optoelectronic devices., 24 pages, 5 figures

We present a physics-based circuit-compatible model for double-gated two-dimensional semiconductor-based field-effect transistors, which provides explicit expressions for the drain current, terminal charges, and intrinsic capacitances. The drain current model is based on the drift-diffusion mechanism for the carrier transport and considers Fermi–Dirac statistics coupled with an appropriate field-effect approach. The terminal charge and intrinsic capacitance models are calculated adopting a Ward–Dutton linear charge partition scheme that guarantees charge conservation. It has been implemented in Verilog-A to make it compatible with standard circuit simulators. In order to benchmark the proposed modeling framework we also present experimental DC and high-frequency measurements of a purposely fabricated monolayer MoS2-FET showing excellent agreement between the model and the experiment and thus demonstrating the capabilities of the combined approach to predict the performance of 2DFETs., The authors would like to thank the financial support of Spanish Government under projects TEC2017-89955-P (MINECO/AEI/FEDER, UE), TEC2015-67462-C2-1-R (MINECO), and RTI2018-097876-B-C21 (MCIU/AEI/FEDER, UE). F.P. and D.J. also acknowledge the support from the European Union’s Horizon 2020 Research and Innovation Program under Grant Agreement No. 785219 GrapheneCore2. A.G. acknowledges the funding by the Consejería de Economía, Conocimiento, Empresas y Universidad de la Junta de Andalucía and European Regional Development Fund (ERDF), ref. SOMM17/6109/UGR. E.G.M. gratefully acknowledges Juan de la Cierva Incorporación IJCI-2017-32297 (MINECO/AEI). A.T.-L. acknowledges the FPU program (FPU16/04043). D.A. acknowledges the Army Research Office for partial support of this work, and the NSF NASCENT ERC and NNCI programs.

An analytical model is proposed to determine the potential and the electron concentration in 1D-confined quantum-well structures. This model is applicable to any kind of asymmetric planar device, such as high-electron-mobility transistors or fully depleted semiconductor-on-insulator FETs. It is based on the solution of the Poisson and Schrodinger equations, under the effective mass approximation, for a triangular potential well, and on the first-order perturbation theory. It is grounded on the physics that governs the device operation and avoids the use of any fitting parameter. The analytical solution considers the wave function penetration into the gate insulator, the effective mass discontinuity at the semiconductor–insulator interfaces, and the Fermi–Dirac statistics. Expressions for the calculation of the subband energies, their corresponding wave functions, as well as the potential profile in the structure are provided. It is demonstrated that our analytical model fits very well the numerical results in all operating regimes from subthreshold to strong inversion for different device sizes and materials.

This work analyzes the electron mobility in few-layer MoS 2 -based metal–insulator-semiconductor field-effect transistors. To do it, the Poisson and Schrodinger equations are self consistently solved using the effective mass approximation to model the six equivalent Λ valleys characteristic of multilayer MoS 2 . The mobility is calculated using the Kubo-Greenwood approach under the momentum relaxation time approximation. The influence of the semiconductor thickness, the temperature and the bias conditions are analyzed. A good agreement with the experimental results presented in the literature is achieved, with electron mobilities ranging between 140 and 200 cm 2 V - 1 s - 1 at T = 300 K .

In this paper, we present a computationally efficient compact model for calculating the charges and gate capacitance of III-V cylindrical nanowire transistors. We proposed an approximation which decouples the Poisson and the Schrodinger equation and addresses the issues of developing a computationally efficient analytical model. Using the proposed approximation, we derived a model suitable for the circuit simulators. The model is physics based and does not include any empirical parameters. The accuracy of the model is verified across nanowires of different sizes and materials using simulation results from a 2D Poisson-Schrodinger solver.

2018 76th Device Research Conference (DRC) : 24-27 June 2018 / [IEEE Electron Device Society (EDS) - ​technical co-sponsor ; Materials Research Society (MRS) - co-sponsor] 76th Device Research Conference, DRC 2018, Santa Barbara, CA, USA, 24 Jun 2018 - 27 Jun 2018; Piscataway, NJ : IEEE 2 Seiten (2018). doi:10.1109/DRC.2018.8442228, Published by IEEE, Piscataway, NJ

The scaling of MOSFET transistors makes the use of new device geometries, such as multigate FETs, a need to solve the limitations of the conventional bulk technology. In this context we introduce an analytical model for square Gate All Around (GAA) MOSFETs with rounded corners including quantum effects. The modeling of rounded corners in GAA and FinFET devices is imperative because there are no perfectly square corners in the cross-section of real devices. In this model the 2D inversion charge distribution function (ICDF) is described analytically for devices of different sizes and for different operation regimes. The model reproduces accurately simulated data obtained with a state-of-the-art simulator that solves self-consistently the Poisson and Schrodinger equations in the devices under consideration. The analytical ICDF is used to better understand the device physics and to calculate the inversion charge centroid and the gate-to-channel capacitance for different device geometries and biases for modeling purposes.

In this brief, the influence of the back-gate biasing, $V_{\text {bg}}$ , on the electron mobility of Si trigates on ultrathin buried oxide is studied, using state of the art scattering models for 2-D confined devices. The variation of the back-gate influence with the device size is analyzed and explained addressing to the charge redistribution in the channel. The lower confinement of larger devices results in strong changes in the electron mobility as $V_{\text {bg}}$ is modified, contrary to what is observed in smaller devices. The charge redistribution due to $V_{\text {bg}}$ also affects the relative influence of the interface walls, which is analyzed in depth. The impact on the mobility of the main scattering mechanisms as a function of $V_{\text {bg}}$ is also discussed.

La futura implementación del Espacio Europeo de Educación Superior (EEES) requiere reflexión sobre la forma de diseñar y desarrollar cursos de formación del profesorado. En esta reflexión, es importante reconsiderar, entre otras cuestiones, el papel de los futuros profe-sores en su propio proceso de aprendizaje y las competencias profesionales que deben des-arrollar en su educación superior. Desde 2004, la Universidad de Granada ha llevado a cabo el desarrollo de experiencias piloto para adaptarse en cierta medida a los programas de este nuevo marco, entre el que se encuentra el grado de Maestro de Educación Primaria. Este grado incluye varios cursos para promover el desarrollo del conocimiento matemático y didáctico de los futuros maestros. En este trabajo analizamos en primer lugar el proceso general de adaptación de dichos cursos. En segundo lugar, describimos su estructura teórica y práctica, con algunos ejemplos de actividades prácticas relacionadas con la Aritmética y el sentido numérico. Finalmente, se discuten algunos resultados de la implementación. Como respuesta al reto que supone la Declaración de Bolonia, desde 2001, más de 175 universidades europeas han trabajado intensamente para crear el Espacio Europeo de Educación Superior (EEES). Este proyecto no sólo es europeo. En 2004, cuando se creó el proyecto latino americano Tuning, muchas universidades latinoamericanas se sumaron a esta reflexión sobre la educación supe-rior guiada por intereses comunes, tales como (a) promocionar la compatibilidad, comparabi-lidad y competitividad en la educación superior, y (b) adaptar los programas a la necesidades de la sociedad tanto en el ámbito local como global (Beneitone, Esquetini, González, Maleta, y la Siufi Wagenaar, 2007). Dentro de este contexto, describimos aquí una experiencia innovadora en el esfuerzo por adaptar la formación en Educación Matemática de los futuros maestros de primaria a las nuevas directivas propuestas, dentro del actual marco jurídico español. Exponemos el proceso de adaptación y los resultados obtenidos en una experiencia piloto desarrollada en el Departamento de Didáctica de la Matemática de la Universidad de Granada.

We simulated the static behavior of scaled FinFETs employing a self-consistent Multi-Subband Ensemble Monte Carlo simulator for non-planar devices. To be able to take into account the three-dimensional device structure, the 2D Schrodinger equation is solved in several cross sections; the coupled solution of the 3D Poisson equation and the 1D Boltzmann transport equation through the ensemble Monte Carlo method guarantees self-consistency. This simulator allowed us to study the effects of different fin aspect ratios while properly taking into account quantum confinement in the plane perpendicular to the transport direction. We studied the transfer characteristic as a function of different geometric parameters, the effect of quantum confinement on the charge distribution and the scaling behavior, down to a channel length of 10 nm.

Graphene/silicon (G/Si) heterojunction based devices have been demonstrated as high responsivity photodetectors that are potentially compatible with semiconductor technology. Such G/Si Schottky junction diodes are typically in parallel with gated G/silicon dioxide (SiO$_2$)/Si areas, where the graphene is contacted. Here, we utilize scanning photocurrent measurements to investigate the spatial distribution and explain the physical origin of photocurrent generation in these devices. We observe distinctly higher photocurrents underneath the isolating region of graphene on SiO$_2$ adjacent to the Schottky junction of G/Si. A certain threshold voltage (V$_T$) is required before this can be observed, and its origins are similar to that of the threshold voltage in metal oxide semiconductor field effect transistors. A physical model serves to explain the large photocurrents underneath SiO$_2$ by the formation of an inversion layer in Si. Our findings contribute to a basic understanding of graphene / semiconductor hybrid devices which, in turn, can help in designing efficient optoelectronic devices and systems based on such 2D/3D heterojunctions., Comment: 25 pages, 5 figures

The electrostatic performance of p-type nanowires (NWs) made of InSb and GaSb, with special focus on their gate capacitance behavior, is analyzed and compared to that achieved by traditional semiconductors usually employed for p-MOS such as Si and Ge. To do so, a self-consistent kp simulator has been implemented to achieve an accurate description of the Valence Band and evaluate the charge behavior as a function of the applied gate bias. The contribution and role of the constituent capacitances, namely the insulator, centroid and quantum ones are assessed. It is demonstrated that the centroid and quantum capacitances are strongly dependent on the semiconductor material. We find a good inherent electrostatic performance of GaSb and InSb NWs, comparable to their Ge and Si counterparts making these III-Sb compounds good candidates for future technological nodes.

In this work we propose an analytical model for the threshold voltage ( V T ) of III–V cylindrical nanowires, that takes into consideration the two dimensional quantum confinement of the carriers, the Fermi–Dirac statistics, the wave-function penetration into the gate insulator and the non-parabolicity of the conduction band structure. A simple expression for V T is obtained assuming some suitable approximations. The model results are compared to those of a 2D self consistent Schrodinger–Poisson solver, demonstrating a good fit for different III–V materials, insulator thicknesses and nanowire sizes with diameter down to 5 nm. The V T dependence on the confinement effective mass is discussed. The different contributions to V T are analyzed showing significant variations among different III–V materials.

A low-field mobility model for square GAA MOSFETs has been developed. The model is analytical and explicit, so it can be used in device simulators and, most importantly, in compact models of these Multi-gate devices for circuit simulation purposes. We have made use of a simulator that includes quantum effects to characterize the electron mobility of square GAA MOSFETs with different sizes for the usual gate voltages and operation regimes. The dependencies with the silicon core lateral size, the inversion charge and the surface roughness are included. The phonon, surface roughness and Coulomb mobility components are modeled separately by means of the Matthiessen rule. Finally, we have performed a comparison between our model and experimental results for validation purposes. We find that the experimental results are well reproduced by our model.

In this letter, we study the electronic properties of InGaAs and Si trigates using the nonparabolic effective mass approximation and up-to-date mobility models. Our comprehensive simulations estimate a strong reduction of the InGaAs electron mobility to values even lower than those achieved with Si. Considering the reduction of the gate capacitance due to the low density-of-states of the III-V alloy, no apparent benefit would be obtained from using InGaAs trigates instead of Si ones unless high quality interfaces can be achieved. We conclude that the potential application of InGaAs trigates as a reference device for future technological nodes is seriously jeopardized by the quality of the semiconductor-insulator interface.

In this paper, we propose a physically based analytical model for the gate capacitance (CG) of III-V nanowire (NW) transistors. The model explicitly accounts for different terms that contribute to CG: the insulator capacitance, the finite density of states, and the charge distribution in the NW. It considers the 2-D quantum confinement of the carriers, the wavefunction penetration into the gate insulator, Fermi-Dirac statistics and the conduction band nonparabolicity, providing analytical expressions for all the capacitance contributions. Furthermore, the behavior and role of the density of states and the charge distribution in the NW are discussed for several materials and the influence of the wavefunction penetration into the gate insulator is also studied. We show that our analytical model is in very good agreement with the numerical solution for different device sizes and materials.

We analyze the behavior of InGaAs Trigate MOSFETs under the influence of a back-gate bias, Vbg. The charge distribution, the body-factor, the threshold voltage and the electron mobility dependences on Vbg are discussed. The InGaAs devices are benchmarked against Si ones demonstrating a higher impact of the back-gate bias for the formers, causing larger body factors and stronger mobility variations.