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The paper reports the in-situ characterization of the creep behavior of flip chip solder balls during 4 point bending test by means of the IForce stress chip. The stress chip technology can measure mechanical stress at the surface of the silicon die. In flip chip configuration, the solder balls are only a few micrometer away from the n-and p-MOS current mirror cells of the stress chip. Hence, relaxation in the solder balls should directly cause measurable effects in these sensor cells. This is demonstrated by 4-point-bending of the flip chip stress chips. A simulation with and without creep material parameter proves the validity of the approach. A time-dependent analysis of the relaxation within the stress cell closest to the solder ball allows the deduction of the relaxation properties from the measurement.

The aim of this paper is to get insight into measurement uncertainties for thermomechanical measurements performed using a piezoresistive silicon-based stress sensor in a standard microelectronic package. All used sensors have the same construction, were produced in the same technological processes at the same time, yet the measurement results show significant distribution. The possible causes for this phenomenon are discussed in this paper. Additionally, Finite Element Method (FEM) model is created and validated, what enables a study of sensitive parameters influencing the measurement uncertainties.

Heat dissipation from three-dimensional (3D) chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m K and 2.8 W/m K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry versus wet filling of filler particles, the optimal bimodal nanosuspension formulation and matrix material feed, and the over-pressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 1500 thermal cycles, as well as to a two-die chip stack. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8 - or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-artcapillary thermal underfill.

Heat dissipation from 3D chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m-K and 2.8 W/m-K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m-K).

Finite Element Simulations of highly integrated and large electronics packages with detailed elastic-plastic material modeling of thousands of solder balls are still challenging tasks for today's computation systems. The complex geometry and mesh and the usage of time consuming creep laws for solder materials makes it nearly impossible to calculate different geometries or process parameters. This paper describes a method to reduce the complexity of the mesh in the region of the solder balls and surrounding underfill with one simple block physically described as a viscoelastic material. Therefore a viscoelastic/plastic behavior of a complex unit cell was modeled in a temperature dependent harmonic frequency sweep or relaxation simulation. The reaction of the unit cell was utilized to synthesize the master curve, Prony coefficients and shift function to an effective material model. Finally an error estimation of the unit cell approach was carried out. Therefore a reliability simulation was modeled replacing the solder balls and the surrounding underfill by the effective material. A flip chip on FR4 model with underfill was used to benchmark the effective material model approach against detailed models without any complexity reduction. The results show that the introduced effective material approach can be used to cut down computation time significantly without losing accuracy in life time prediction.

To satisfy the increasing need in today's industry for high performance, more complex chips are being designed. These chips, when integrated in 3D packages, have a high energy density and require new and innovative cooling strategies as many of them are designed as flip-chip assemblies, usually requiring back-side cooling. Classical underfills currently used offer poor thermal conductivity. But cooling through the underfill would enable cost-efficient and low complexity cooling solutions. For this purpose, thermal underfills with percolating fillers and necks are currently under development. They are to provide a significant improvement in thermal conductivity to classical capillary underfills and will find applications in, for example, 3D integrated packages to improve heat dissipation. The idea behind the percolating thermal underfill (PTU) comprises a sequential joint forming process ensuring a high fill fraction. Although flip chip technology has been well described, the addition of the neck based percolating underfill could entail several new thermo-mechanical reliability concerns that need to be studied using a physics of failure approach, since the PTU exhibits vastly different thermo-mechanical behavior, giving rise to possible new failure mechanisms and locations. This paper in particular deals with FE simulations carried out to understand different key aspects of the thermal underfill and to study the effects of the increased underfill stiffness at these locations. The simulations are implemented using detailed elastic, plastic, visco-elastic and visco-plastic material data. In case of larger models a complexity reduction is required and implemented by using effective material data to improve computational time.

Percolating and neck-based thermal underfills with significant improvements in thermal conductivity compared with capillary underfills are currently under development. They could be applied between dies to improve the heat dissipation through a 3D chip stack. In this parametric study, we provide insights into the thermal, mechanical, thermo-mechanical and electrical properties achievable by this new composite material class. The primary objective of the investigation is the linear buckling phase of monodisperse spherical filler particles confined between two parallel plates with a fill fraction range of 48.7% to 61.3% as observed by experiment. The introduction of necks between the point contacts of the filler particles had the most significant impact on the composite effective material properties, resulting in an increase in thermal conductivity, stiffness and a drop in the thermal expansion coefficient. The high stiffness could cause delamination of the underfill in chip corners because of high shear forces and hence may have to be mitigated. Finally, two design points for the composite were proposed, respecting the target values for the percolating and neck-based thermal underfill, with a predicted effective thermal conductivity of 1.9 and 3.6 W/m-K.

This paper describes a method used for experimental real-time monitoring of thermo-mechanical stress build-up during integrated circuit encapsulation. To detect the stress variations during molding, special stress measuring chips were employed. The working principle of the stress chip is based on the piezoresistive sensors embedded on the surface in a 6 by 6 matrix distribution. [1]

The integration of smart systems into hybrid structures is one of the challenges addressed by the project MERGE - the cluster of excellence on Technologies for Multifunctional Lightweight Structures. As a first example, a sensor system is integrated that is able to explore the thermo-mechanical conditions these systems will typically be exposed to. After briefly describing the sensor system, the paper focuses on the results of the encapsulation step as part of the fabrication process mounting the sensor chip on the test board. The sensor system measures the mechanical stresses during and after transfer molding. In particular, the in-plane components on the chip surface were recorded with high accuracy [1, 2]. Based on these informations, material parameters have been deduced by combining experimental and simulation methods within a Design of Experiment (DoE) study. During the encapsulation process, two sets of effects induce stress into the package simultaneously. On one hand, the coefficients of thermal expansion (CTE) lead to a thermal shrinkage of the materials during cooling from the curing to room temperature. On the other hand, the volume also decreases when the epoxy mold compound (EMC) is cured from its fluid into the final solid stage. This effect is called chemical cure shrinkage [3]. Separating both effects is really a challenge. The method shown in this paper allows quantifying the corresponding material parameters by combining the stress measurements with numerical parameter identification. Based on this method, the investigation on failure modes and reliability of the integrated smart systems can be improved.

To ensure functionality and integrity of electronic package interconnects, underfill materials are designed to meet a desired stiffness that bridges the thermal expansion behavior of die, substrates and interconnects. The underfill protects the interconnects from thermal strains and environmental influences. Recently, the thermal conductivity became a critical parameter too, to efficiently dissipate heat from 3D chip stacks. Accordingly, the particle loading is increased beyond the percolation threshold, which was demonstrated by sequentially fabricated materials with a 5fold thermal conductivity improvement. This paper explores the thermo-mechanical properties of the novel percolating thermal underfills considering alumina filler particles. The changing behavior of underfill composites has been well described for various fillers and matrices both theoretically and experimentally. But percolation was excluded so far for lack of relevance. We compare the numerical predictions of composites' Young's moduli around the filler percolation threshold to known effective-medium approximation bounds of polydisperse materials. The simulations were based on 3D unit cells of the face centered cubic packing in different lattice orientations and consider both filler and matrix materials. A significant change in characteristics is observed close to percolation. However, the 100 and the 110 lattice orientations give a 5% Young's modulus difference only. The numerical predictions are within effective-medium approximation bounds, but appear closer to either upper or lower bounds depending on the filler fraction. The presented results extend the possible thermo-mechanical parameter space of conventional underfills to percolating composites.

The experimental observation of the actual thermo mechanical weak points in microelectronics packages remains a big challenge. Recently, a stress sensing system has been developed by a publicly funded project that allows measuring the magnitudes and the distribution of the stresses induced in the silicon dies by thermo-mechanical loads. Some application experiments will be presented, e.g. thermal loads, 4-point bending on CoB setups, and moisture swelling. The stress chip was detecting CTE mismatch, transition temperature, delamination, creep relaxations and volume swelling of moisture loads. All measurements are supplemented by finite element simulations based on calibrated models for in-depth analysis and for extrapolating the stress results to sites of the package that cannot measured directly. The methodology of closely combining stress measurements at inner points and FE simulation presented in this paper has been able to validate the stress sensing system for tasks of comprehensive design and process characterization as well as for health monitoring. It allows achieving both, a substantial reduction in time to- market and a high level of reliability under service conditions, as needed for future electronics and smart systems packages.

The experimental observation of the actual thermo-mechanical weak points in microelectronics packages remains a big challenge. Recently, a stress sensing system has been developed by the publicly funded project that allows measuring the magnitudes and the distribution of the stresses induced in the silicon dies by thermo-mechanical loads. The paper reports investigations on industrial QFN packages of 6×6×1mm3 in size. The stress field has been recorded before and after soldering the component to the PCB as well as during thermal cycle and bending tests. Onset and evolution of internal damages have been detected by changes in the stress at the chip surface due to degradations of materials or interfaces within the course of the thermal cycling test. Applying 3-D x-ray computer tomography, the damages inside the packages have been validated at several stages during the test. All measurements are supplemented by finite element simulations based on calibrated models for in-depth analysis and for extrapolating the stress results to sites of the package that are not measured directly. The methodology of closely combining stress measurements and FE simulation presented in this paper has been able to validate the stress sensing system for tasks of comprehensive design and process characterization as well as for health monitoring. It allows achieving both, a substantial reduction in time-to-market and a high level of reliability under service conditions, as needed for future electronics and smart systems packages.

Three different methods of stress measurement with strong spatial resolution are presented. They base on stress relief techniques caused by focused ion beam milling, on altered electron backscattering by deformed lattices and on Stokes line shift measurements by Raman spectroscopy. The capability of these methods is demonstrated by their application to typical MEMS structures. A comparison between the methods is performed in order to outline potentials and limitations.

This paper investigates different stress and strain measurement methods usable during packaging of electronic systems. By applying stress measurement chips, embedded fiber optic Bragg grating (FBG) sensors and pressure sensitive multilayers it is possible to determine the stress condition on the surface of silicon chips, on various substrates and within epoxy polymers.

Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/5920); International audience; Prime concerns in designing liquid cooling solutions are performance, reliability and price. To that end a one-phase liquid cooling concept is proposed, where all pumps, valves and piping are fully integrated on board level. Only low-cost organic board technology and SMT processes are used in the design. This paper addresses the key issues of such a concept together with some numerical and first experimental results. It is highlighted that for such a concept a special type of membrane pump with adequate valve technology is especially suit- able. Design guidelines as to its performance are given. Eventually, the obtained results are eval- uated with respect to the requirements and nec- essary further developments are commented on to make the concept eligible for the cost-performance- sector.

The 3D-packaging technology makes it possible to stack the PCBs on top of each other and thus make full use of the third dimension. A unique space between the stacked PCB layers enables a reproducible technology without shortcuts or unconnected bumps. New applications in 3D-PDB-packages, called PCBMEMS can be realized with the combination of electric bumps and solder rings. The paper shows an fluidic cooled 11-PCB-layer with high power components. Water channels in the PCB-package dissipate the heat from the inside of the package to the environment. Heat dissipation is a bigger challenge for stacks of 3D-packages than for normal printed circuit boards (PCBs). This research paper investigates some design suggestions for a better heat dissipation. On the basis of this research paper, it becomes possible to choose the best suited PCB design. The experimental results were compared to thermal simulation results. The results of the measurements and FEM simulations show, how important it is to combine the electrical and geometrical functions of 3D packages with a thermally optimized PCB design. A better heat spreading and conduction in a 3D package makes the stack more reliable at higher power dissipation.