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Low‐band gap semiconductor polymer materials play a crucial role in the field of organic optoelectronics. In this context, a series of low‐band gap polymers containing thienopyrazine as the acceptor and cyclofluorene–bithiophene as the donor were synthesized and utilized in resistive random access memory (RRAM) devices. These memory devices consistently exhibit nonvolatile flash memory behavior. Remarkably, all three polymers demonstrate stability even after 1000 cycles without significant fluctuations. Notably, the three polymer‐based devices also exhibit excellent ternary memory performance, with current ratios of 1:102.8:104, 1:101.3:103.9, and 1:101.8:103.6. Furthermore, the photoelectric properties of the three polymers and the conduction mechanisms of the memory devices were thoroughly discussed. [ABSTRACT FROM AUTHOR]

Non‐volatile charge‐trap flash memory (CTM) co‐located with heterogeneous III‐V/Si photonics is demonstrated. The wafer‐bonded III‐V/Si CTM cell facilitates non‐volatile optical functionality for a variety of devices such as Mach–Zehnder Interferometers (MZIs), asymmetric MZI lattice filters, and ring resonator filters. The MZI CTM exhibits full write/erase operation (100 cycles with 500 states) with wavelength shifts of Δλnon‐volatile = 1.16 nm (Δneff,non‐volatile ≈ 2.5 × 10−4) and a dynamic power consumption <20 pW (limited by measurement). Multi‐bit write operation (2 bits) is also demonstrated and verified over a time duration of 24 h and most likely beyond. The cascaded second order ring resonator CTM filter exhibited an improved ER of ≈7.11 dB compared to the MZI and wavelength shifts of Δλnon‐volatile = 0.041 nm (Δneff, non‐volatile = 1.5 × 10−4) with similar pW‐level dynamic power consumption as the MZI CTM. The ability to co‐locate photonic computing elements and non‐volatile memory provides an attractive path toward eliminating the von‐Neumann bottleneck. [ABSTRACT FROM AUTHOR]

With the rise of on‐device artificial intelligence (AI) technology, the demand for in‐memory comptuing has surged for data‐intensive tasks on edge devices. However, on‐device AI requires high‐density, low‐power memory‐based computing to efficiently handle large data volumes. Here, this study proposes a reliable multilevel, high gate‐coupling ratio memory device with MoS2 channel tailored for high‐density 3D NAND Flash‐based in‐memory computing. The MoS2 channel, featured by its small bandgap and high‐mobility, facilitates reliable memory window of approximately 8 V thanks to erase operation through hole injection. This not only suppresses vertical charge loss but also alleviates the burden on voltage generator circuits, indicating the suitability of MoS2 as channel material for 3D NAND Flash architecture. Additionally, a low‐k (≈2.2) tunneling layer deposited via initiated chemical vapor deposition increases the gate‐coupling ratio, thereby reducing the operating voltage. Utilizing Au nanoparticles as the charge storage layer, MoS2 memory devices show synaptic plasticity with 6‐bit, endurance (104 cycles), read disturbance (105 cycles), and retention times (105 s). Furthermore, device‐to‐system simulations for neural networks based on MoS2‐memory devices have successfully achieved a fingerprint recognition of 95.8%. These results provide the foundation to develop multi‐bit MoS2‐memory devices for AI accelerators and 3D NAND Flash memory. [ABSTRACT FROM AUTHOR]

Flash memory, ubiquitous in diverse electronic devices, confronts persistent challenges stemming from inherent errors that jeopardize data integrity. This research situates itself at the intersection of these challenges and advancements, proposing an inventive error correction coding framework that harnesses the unique capabilities of analysis with a hybrid error control coding (HECC) approach. In the proposed work, a mathematical model aimed at enhancing the flash memory by identifying the error pattern within the pages using the discrete fourier transform (DFT). By incorporating distinctive DFT mathematical properties, the proposed technique intends to improve flash memory error correction beyond traditional methods. The flash storage defect detection and rectification results with hybrid error correction coding achieved bit error rate (BER) of 4.3e-6, latency 14.1, mean 15.1 and standard deviation 1.0. Error correction efficiency 98% and storage overhead 10%. With this approach results are significantly improving the error correction efficiency, reduce storage overhead and enhanced adaptability to diverse error patterns. [ABSTRACT FROM AUTHOR]

Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost. The reliability property is becoming an important factor for NAND flash memory with multi-level-cell (MLC) modes like triple-level-cell (TLC) or quad-level-cell (QLC), which is seriously affected by the intervals between program (P) and erase (E) operations during P/E cycles. In this work, the impacts of the intervals between P&E cycling under different temperatures and P/E cycles were systematically characterized. The results are further analyzed in terms of program disturb (PD), read disturb (RD), and data retention (DR). It was found that fail bit counts (FBCs) during the high temperature (HT) PD process are much smaller than those of the room temperature (RT) PD process. Moreover, upshift error and downshift error dominate the HT PD and RT PD processes, respectively. To improve the memory reliability of 3D CT TLC NAND, different intervals between P&E operations should be adopted considering the operating temperatures. These results could provide potential insights to optimize the lifetime of NAND flash-based memory systems. [ABSTRACT FROM AUTHOR]

Increasing the bit density in 3D NAND flash memory involves reducing the pitch of ON (Oxide-Nitride) molds in the Z-direction. However, this reduction drastically increases Z-interference, adversely affecting cell distribution and accelerating degradation of reliability limits. Previous studies have shown that programming from the top word line (WL) to the bottom WL, instead of the traditional bottom-to-top approach, alleviates Z-interference. Nevertheless, detailed analysis of how Z-interference varies at each WL depending on the programming sequence remains insufficient. This paper investigates the causes of Z-interference variations at Top, Middle, and Bottom WLs through TCAD analysis. It was found that as more electrons are programmed into WLs within the string, Z-interference variations increase due to increased resistance in the poly-Si channel. These variations are exacerbated by tapered vertical channel profiles resulting from high aspect ratio etching. To address these issues, a method is proposed to adjust bitline biases during verification operations of each WL. This method has been validated to enhance the performance and reliability of 3D NAND flash memory. [ABSTRACT FROM AUTHOR]

Keyword search is the most ordinary tool in patent offices; however, for more advanced research, free software is not presented on their websites. Thus, this paper has the purpose to provide a data-mining framework for patent documents, linking the natural language processing techniques and data analysis algorithms. The system has two main goals: the analysis of technological prospection and the evaluation of similarities among patents through titles and abstracts. For numerical experiments, we used the base of the US Patent and Trademark Office, with over a million documents. Analysing patents about TFT-LCD, Flash Memory and PDA, from 2010 to 2018, with S-Curve it was observed that the last two technologies decline. Using a cloud of words, it was possible to see the phone's evolution, from 2010 to 2015. To evaluate the degree of similarity among patents, we investigated Latent Semantic Analysis (LSA), Word2vec, Word Mover's Distance (WMD), in three different study cases. In addition, these methods were compared with the classical Jaccard index. Numerical results show that LSA and WMD obtained similar patent indications, and the Jaccard index presented different indications from the other three. [ABSTRACT FROM AUTHOR]

This study investigates the impact of oxide/nitride (ON) pitch scaling on the memory performance of 3D NAND flash memory. We aim to enhance 3D NAND flash memory by systematically reducing the spacer length (Ls) and gate length (Lg) to achieve improved memory characteristics. Using TCAD simulations, we evaluate the effects of Ls and Lg scaling on the program speed, erase speed, and Z-interference. Furthermore, we examine the influence of concave and convex channel structures in the context of Ls and Lg scaling. By analyzing the distributions of electron and hole-trapped charges, we provide insights into optimizing the trade-offs between the memory window and retention characteristics. This research offers valuable guidelines for improving the reliability and performance of 3D NAND flash memory through a systematic analysis of spacer and gate length scaling. [ABSTRACT FROM AUTHOR]

The typical procedure for Earth Observation Nanosatellites involves the sequential steps of image capture, onboard storage, and subsequent transmission to the ground station. This approach places significant demands on onboard resources and encounters bandwidth limitations; moreover, the captured images may be obstructed by cloud cover. Many current deep-learning methods have achieved reasonable accuracy in cloud detection. However, the constraints posed by nanosatellites specifically in terms of memory and energy present challenges for effective onboard Artificial Intelligence implementation. Hence, we propose an optimized tiny Machine learning model based on the U-Net architecture, implemented on STM32H7 microcontroller for real-time cloud coverage prediction. The optimized U-Net architecture on the embedded device introduces Depthwise Separable Convolution for efficient feature extraction, reducing computational complexity. By utilizing this method, coupled with encoder and decoder blocks, the model optimizes cloud detection for nanosatellites, showcasing a significant advancement in resource-efficient onboard processing. This approach aims to enhance the university nanosatellite mission, equipped with an RGB Gecko imager camera. The model is trained on Sentinel 2 satellite images due to the unavailability of a large dataset for the payload imager and is subsequently evaluated on gecko images, demonstrating the generalizability of our approach. The outcome of our optimization approach is a 21% reduction in network parameters compared to the original configuration and maintaining an accuracy of 89%. This reduction enables the system to allocate only 61.89 KB in flash memory effectively, resulting in improvements in memory usage and computational efficiency. [ABSTRACT FROM AUTHOR]

When multiple apps with different I/O priorities share a high-performance SSD, it is important to differentiate the I/O QoS level based on the I/O priority of each app. In this paper, we study how a modern flash-based SSD should be designed to support priority-aware read performance differentiation. From an in-depth evaluation study using 3D TLC SSDs, we observed that existing FTLs have several weaknesses that need to be improved for better read performance differentiation. In order to overcome the existing FTL weaknesses, we propose ReadGuard, a novel priority-aware SSD management technique that enables an FTL to manage its blocks in a fully read-latency-aware fashion. ReadGuard leverages a new read-latency-centric block quality marker that can accurately distinguish the read latency of a block and ensures that higher-quality blocks are used for higher-priority apps. ReadGuard extends an existing suspend/resume technique to handle collisions among reads. Our experimental results show that a ReadGuard-enabled SSD is effective in supporting differentiated read performance in modern 3D flash SSDs. [ABSTRACT FROM AUTHOR]

Smart healthcare systems integrated with advanced deep neural networks enable real‐time health monitoring, early disease detection, and personalized treatment. In this work, a novel 3D AND‐type flash memory array with a rounded double channel for computing‐in‐memory (CIM) architecture to overcome the limitations of conventional smart healthcare systems: the necessity of high area and energy efficiency while maintaining high classification accuracy is proposed. The fabricated array, characterized by low‐power operations and high scalability with double independent channels per floor, exhibits enhanced cell density and energy efficiency while effectively emulating the features of biological synapses. The CIM architecture leveraging the fabricated array achieves high classification accuracy (93.5%) for electrocardiogram signals, ensuring timely detection of potentially life‐threatening arrhythmias. Incorporated with a simplified spike‐timing‐dependent plasticity learning rule, the CIM architecture is suitable for robust, area‐ and energy‐efficient in‐memory arrhythmia detection systems. This work effectively addresses the challenges of conventional smart healthcare systems, paving the way for a more refined healthcare paradigm. [ABSTRACT FROM AUTHOR]

In this research, we analyze the real data in the NAND Flash memory industry using a control chart. There are thousands of electrical measures for each NAND Flash memory chip. We monitor these data through a control chart to ensure that the manufacturing process is in control. For better interpretability, we apply a univariate control chart technique to each variable. However, most existing control charts, such as the EWMA chart, do not include between-subgroup variations but only within-subgroup variations. They often obtain too narrow control limits for some variables, which leads too many subgroups to fall outside the control limits. To overcome this issue, we apply a control chart under a mixed-effects modeling framework to include both within-subgroup and between-subgroup variations. Additionally, the EWMA chart assumes that all the items are normally distributed; however, we frequently encounter that a normal assumption is violated. To overcome this limitation, we apply a robust approach based on a nonparametric sign chart. Furthermore, we introduce a p-value combination method to increase the statistical power for the gradual change detection of a statistical process. Our study show that the proposed control chart can efficiently monitor the real data in the NAND Flash memory industry. [ABSTRACT FROM AUTHOR]

Brain-inspired resistive random-access memory (RRAM) technology is anticipated to outperform conventional flash memory technology due to its performance, high aerial density, low power consumption, and cost. For RRAM devices, metal oxides are exceedingly investigated as resistive switching (RS) materials. Among different oxides, tin oxide (SnOx) received minimal attention, although it possesses excellent electronic properties. Herein, we demonstrate compliance-free, analog resistive switching behavior with several stable states in Ti/Pt/SnOx/Pt RRAM devices. The compliance-free nature might be due to the high internal resistance of SnOx films. The resistance of the films was modulated by varying Ar/O2 ratio during the sputtering process. The I–V characteristics revealed a well-expressed high resistance state (HRS) and low resistance states (LRS) with bipolar memristive switching mechanism. By varying the pulse amplitude and width, different resistance states have been achieved, indicating the analog switching characteristics of the device. Furthermore, the devices show excellent retention for eleven states over 1000 s with an endurance of > 100 cycles. [ABSTRACT FROM AUTHOR]

Brain-inspired resistive random-access memory (RRAM) technology is anticipated to outperform conventional flash memory technology due to its performance, high aerial density, low power consumption, and cost. For RRAM devices, metal oxides are exceedingly investigated as resistive switching (RS) materials. Among different oxides, tin oxide (SnOx) received minimal attention, although it possesses excellent electronic properties. Herein, we demonstrate compliance-free, analog resistive switching behavior with several stable states in Ti/Pt/SnOx/Pt RRAM devices. The compliance-free nature might be due to the high internal resistance of SnOx films. The resistance of the films was modulated by varying Ar/O2 ratio during the sputtering process. The I–V characteristics revealed a well-expressed high resistance state (HRS) and low resistance states (LRS) with bipolar memristive switching mechanism. By varying the pulse amplitude and width, different resistance states have been achieved, indicating the analog switching characteristics of the device. Furthermore, the devices show excellent retention for eleven states over 1000 s with an endurance of > 100 cycles. [ABSTRACT FROM AUTHOR]

Split-gate embedded Flash memory technology has been around for decades and has become the standard application for a wide range of devices such as microcontrollers and smart cards. Among them, due to a number of advantages, SuperFlash (SF) produced by Silicon Storage Technology is the most widely used nonvolatile memory technology. In this paper, the results of a study of the structure of memory cells (MCs) are presented and the principle of their operation, as well as the main technological stages of the production process of forming transistor structures, is discussed. [ABSTRACT FROM AUTHOR]

Modern microcontroller units (MCUs) often feature integrated flash memory, which has been found to be vulnerable to hardware attacks. This type of memory is used to store critical data, including firmware, passwords, and cryptographic keys, making it a valuable target for attackers. Recent research has demonstrated the use of laser fault injection (LFI) during runtime to corrupt firmware by targeting the flash memory during read operations. However, these faults are non-permanent, as they only affect the read copies of the data without altering the actual data stored in the flash memory, following a bit-set fault model induced on a single bit. In our work, we extend this fault model to the flash memory of a 32-bit MCU, allowing us to induce permanent faults by compromising the stored data during read operations. In addition, we leverage photoemission analysis for target identification and characterization, enhancing the precision of our attack. By utilizing a double-spot LFI technique, we are able to concurrently induce permanent bit-set faults at two distinct locations in the flash memory, increasing the complexity and effectiveness of the attack. We also provide a practical example of how this fault model can be applied, wherein we iteratively change all 32 bits of a password to logic '1', successfully bypassing a basic counter for login attempts. It is important to note, however, that there are physical limitations associated with using multi-laser spots in this context, which we thoroughly discuss in our research. Nonetheless, our approach presents a powerful method for exploiting vulnerabilities in flash memory of MCUs, underscoring the need for robust security measures to protect critical data and mitigate the risks associated with hardware attacks. [ABSTRACT FROM AUTHOR]

Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems. [ABSTRACT FROM AUTHOR]

An engineering approach was applied to modify the core layers of charge-trapping flash (CTF) memory—the blocking layer, charge-trapping layer, and tunneling layer. The doping of Ti in the charge-trapping layer and the use of Si-doped HfO2 for the tunneling layer could optimize charge capture and leakage control. This design enhances programming and erasing speeds and increases overall device stability by creating more corner fields and using the Coulomb blockade effect. Experimental results demonstrate a larger memory window and better charge retention for the new device at the same charge-trapping layer thickness. These findings signify the advancement of the new CTF memory in balancing fast programming and long-term charge retention. The long-standing contradiction between charge capturing and retention could be partially resolved by using this engineering method. [ABSTRACT FROM AUTHOR]

Physical attacks, and among them fault injection attacks, are a significant threat to the security of embedded systems. Among the means of fault injection, laser has the significant advantage of being extremely spatially accurate. Numerous state-of-the-art studies have investigated the use of lasers to inject faults into a target at run-time. However, the high precision of laser fault injection comes with requirements on the knowledge of the implementation and exact execution time of the victim code. The main contribution of this work is the demonstration on experimental basis that it is also possible to perform laser fault injection on an unpowered device. Specifically, we targeted the Flash non-volatile memory of a 32-bit microcontroller. The advantage of this new attack path is that it does not require any synchronisation between the victim and the attacker. We provide an experimental characterization of this phenomenon with a description of the fault model from the physical level up to the software level. Finally, we applied these results to carry out a persistent fault analysis on a 128-bit AES with a particularly realistic attacker model which reinforces the interest of the PFA.

The emergence of embedded magnetic random-access memory (MRAM) and its integration in mainstream semiconductor manufacturing technology have created an unprecedented opportunity for engineering computing systems with improved performance, energy efficiency, lower cost, and unconventional computing capabilities. While the initial interest in the existing generation of MRAM—which is based on the spin-transfer torque (STT) effect in ferromagnetic tunnel junctions—was driven by its nonvolatile data retention and lower cost of integration compared to embedded Flash (eFlash), the focus of MRAM research and development efforts is increasingly shifting toward alternative write mechanisms (beyond STT) and new materials (beyond ferromagnets) in recent years. This has been driven by the need for better speed vs density and speed vs endurance trade-offs to make MRAM applicable to a wider range of memory markets, as well as to utilize the potential of MRAM in various unconventional computing architectures that utilize the physics of nanoscale magnets. In this Perspective, we offer an overview of spin–orbit torque (SOT) as one of these beyond-STT write mechanisms for the MRAM devices. We discuss, specifically, the progress in developing SOT-MRAM devices with perpendicular magnetization. Starting from basic symmetry considerations, we discuss the requirement for an in-plane bias magnetic field which has hindered progress in developing practical SOT-MRAM devices. We then discuss several approaches based on structural, magnetic, and chiral symmetry-breaking that have been explored to overcome this limitation and realize bias-field-free SOT-MRAM devices with perpendicular magnetization. We also review the corresponding material- and device-level challenges in each case. We then present a perspective of the potential of these devices for computing and security applications beyond their use in the conventional memory hierarchy. [ABSTRACT FROM AUTHOR]

In this study, the channel potential of inhibited strings in 3D NAND flash memory using a bandgap-engineered tunneling oxide (BE-TOX) structure is analyzed. The equivalent oxide thickness (EOT) of the structure using BE-TOX was designed to be the same as the conventional 3D NAND flash memory, and the channel potentials of the down coupling phenomenon (DCP) and natural local self-boosting (NLSB) effect were analyzed. As a result, the BE-TOX structure was confirmed to have a higher channel potential in the DCP and NLSB than the conventional structure, making it relatively effective for program disturbance. The main reason for the difference in the channel potential between the BE-TOX and conventional structures is that adjacent cells have different threshold voltages (Vth). When the same program voltage (VPGM) and program time (TPGM) were applied during the program operation, Vth decreased in the BE-TOX structure, which increased the channel potential when DCP and NLSB occurred. Finally, a simulation was conducted by varying the thicknesses of the oxide and nitride in the BE-TOX structure. Despite the EOT being fixed and the thicknesses of both nitride and oxide being varied, the channel potential was affected. [ABSTRACT FROM AUTHOR]

This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two‐input and four‐input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform‐based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft‐core processor on a quantum processing unit. [ABSTRACT FROM AUTHOR]

A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Based on the proposed partial decoding algorithm, a prototype decoder is implemented in a 65 nm CMOS process to decode a 4 KB LDPC code. The proposed decoder reduces energy consumption by 93% compared to the conventional LDPC decoding architecture at maximum. [ABSTRACT FROM AUTHOR]

Vibration analysis is commonly used to assess machinery conditions, earthquake detection, and structural monitoring. Commercially available DAQs (Data Acquisition Systems) feature high costs and limited versatility in terms of end-user hardware/firmware customization, making it difficult to adapt them to the input signal features and add supplementary functionalities. Hence, this research aims to develop a custom acquisition board for detecting vibration signals via IEPE (Integrated Electronic Piezoelectric) sensors, considering the limitations of commercially available systems, and building upon solutions found in the literature. The DAQ board was intended for remote vibration monitoring of infrastructure and machinery for industrial applications, allowing the implementation of predictive maintenance strategies. The proposed DAQ board has two independent and fully configurable channels, which can be set for acquiring signals from IEPE sensors or generic voltage sources. The DAQ board relies on the STM32F401 microcontroller to manage the acquisition from high-speed ADCs, process data, and store them in mass memory (SD card). During acquisition, the DAQ implements a batch acquisition strategy based on a buffer flash memory for temporarily storing ADCs data, which are iteratively poured into mass memory. Also, the board has Bluetooth connectivity to transmit acquired data and receive commands remotely. A prototype of the DAQ board was developed and tested with several waveforms, including vibration signals. The tests showed that the board can acquire vibration signals and compute the FFT onboard. The DAQ demonstrated a good balance between performance, accuracy, flexibility, and cost, making it suitable for several industrial applications and allowing for scalability and integration potential. [ABSTRACT FROM AUTHOR]

An increase in the demand for artificial intelligence is leading to advanced research in the field of neuromorphic systems, which imitate human brain functions with the hope of increasing computational speed and lowering power consumption. Especially, the development of energy‐efficient and reliable synaptic devices is critical as synapses are fundamental building blocks of neuromorphic systems. In this study, by adjusting the charge injection pathway of conventional flash memory devices, a lateral migration‐based synaptic device is proposed. Using the efficient program/erase method, the proposed device is operable at a significantly low voltage while maintaining formidable retention and endurance characteristics. Furthermore, an efficient hybrid off‐chip/on‐chip training method using the proposed device is presented. The results demonstrate a variation‐robust neuromorphic system, indicating the superiority of the proposed device. [ABSTRACT FROM AUTHOR]

The advent of multi-valued logic (MVL) systems provides considerable improvements in energy consumption and computational efficiency compared to binary logic systems. Using resistive random-access memory (RRAM) and carbon nanotube field effect transistors (CNTFETs), this manuscript presents a new design method for ternary logic gates (standard ternary inverter (STI), ternary NOR, and ternary NAND) and some arithmetic circuit applications are implemented based on the proposed ternary logic gates. The simulations of the proposed circuits are carried out in Synopsis HSPICE software by employing 32-nm Stanford CNTFET technology along with the Stanford RRAM model. The robustness of the designed CNTFET-RRAM STI circuit is investigated for variations in process parameters. Simulation results verify that the proposed designs outperform other CNTFET based ternary logic circuits in terms of number of components, power consumption, delay and power delay product (PDP). Furthermore, a reduced change is perceived with respect to power consumption and PDP of the presented logic gates with process deviation, and variations in supply voltage, temperature, capacitance and frequency. The presented STI, TNAND, TNOR, ternary half adder (THA) and ternary multiplier (TMUL) circuits exhibit an improvement in PDP with less transistor count as compared to the other existing designs in the literature. [ABSTRACT FROM AUTHOR]

This paper presents an innovative approach to alleviate Z-interference in 3D NAND flash memory by proposing an optimized confined nitride trap layer structure. Z-interference poses a significant challenge in 3D NAND flash memory, especially with the reduction in cell spacing to accommodate an increased number of vertically stacked 3D NAND flash memories. While the confined nitride trap layer device designed for complete isolation of the trapping layer in three dimensions effectively reduces Z-interference, the results showed substantial variations based on the confined structure. To clarify this issue, we compared three distinct confined nitride trap layer structures and investigated their impact on Z-interference. Our findings indicate that the rectangle structure exhibited the most significant mitigation, implying that differences in the electric field applied to the poly silicon channel, which is influenced by the structure, and the increase in effective channel length are effective strategies for alleviating Z-interference. The proposed structure undergoes a comprehensive examination through technology computer-aided design (TCAD) simulations. Additionally, we introduce a practical process flow designed to minimize Z-interference. [ABSTRACT FROM AUTHOR]

In recent years, non-volatile memory elements have become highly appealing for memory applications to implement a new class of storage memory that could replace flash memories in sequential logic applications, with features such as compactness, low power, fast processing speed, high endurance, and retention. The memristor is one such non-volatile element that fits the fundamental blocks of sequential logic circuits, the latch and flip-flop; hence, in this article, a non-volatile latch architecture using memristor ratioed logic (MRL) inverter and CMOS components is focused, with an additional memristor as a memory element. A Verilog-A model was used to create the memristor element. The simulation findings validated the compact, low-voltage, and reliable design of the latch design. We evolved in technology enough to create a master-slave flip-flop and arrange it to function as a counter and a shift register. Power, number of elements, cell size, energy, programming time, and robustness are compared to comparable non-volatile topologies. The proposed non-volatile latch proves non-volatility and can store data with a 24% reduction in power consumption and a near 10% reduction in area. [ABSTRACT FROM AUTHOR]

In order to successfully achieve mass production in NAND flash memory, a novel test procedure has been proposed to electrically detect and screen the channel hole defects, such as Not-Open, Bowing, and Bending, which are unique in high-density 3D NAND flash memory. Since channel hole defects lead to catastrophic failure (i.e., malfunction of basic NAND operations), detecting and screening defects in advance is one of the key challenges of guaranteeing the quality of flash products in the NAND manufacturing process. Based on analysis of the physical and electrical mechanisms of the channel hole defect, we have developed a two-step test procedure that consists of pattern-based and stress-based screen methodologies. By optimizing test patterns depending on the type of defect, the pattern-based screen is effective for detecting the type of Hard channel hole defects. The stress-based screen is carefully implemented to detect hidden Soft channel hole defects without degrading the reliability of NAND flash memory. In addition, we have attempted to further optimize the current version of our technique to minimize test time overhead, thus enabling 72.2% improvement in total test time. Experimental results using real 160 3D NAND flash chips show that our technique can efficiently detect and screen out various types of channel hole defects with minimum test time and negligible degradation in the flash reliability. [ABSTRACT FROM AUTHOR]

This paper is an extended version of a previously reported conference paper regarding a low-power design for NAND Flash. As the number of bits per NAND Flash die increases with cost scaling, the IO data path speed increases to minimize the page access time with a scaled CMOS in IOs. The power supply for IO buffers, namely, VDDQ, decreases from 3 V to 1.2 V, accordingly. In this paper, the way in which a reduction in VDDQ can contribute to power reduction in the BL path is discussed and validated. Conventionally, a BL voltage of about 0.5 V has been supplied from a supply voltage source (VDD) of 3 V. The BL path power can be reduced by a factor of VDDQ to VDD when the BL voltage is supplied by VDDQ. To maintain a sense margin at the sense amplifiers, the supply source for BLs is switched from VDDQ to VDD before sensing. As a result, power reduction and an equivalent sense margin can be realized at the same time. The overhead of implementing this operation is an increase in the BL access time of about 2% for switching the power supply from VDDQ to VDD and an increase in the die size of about 0.01% for adding the switching circuit, both of which are not significant in comparison to the significant power reduction in the BL path power of the NAND die of about 60%. The BL path is then designed in 180 nm CMOS to validate the design. When the cost for powering the SSD becomes quite significant, especially for data centers, an additional lower voltage supply, such as 0.8 V, dedicated to BL charging for read and program verifying operations may be the best option for future applications. [ABSTRACT FROM AUTHOR]