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This paper investigates the single event upset sensitivity of Bulk SRAMs for terrestrial applications. The technology sensitivity is analyzed with both quasi-monoenergetic neutron and proton experiments in an energy range from 14 to 180 MeV. Analytical and simulation based correction methods of the neutron cross section are presented and validated. Then, neutron and proton cross section are compared. Soft Error Rate (for the terrestrial neutron spectrum) calculated with either proton or quasi-monoenergetic neutron data are also presented and compared. Index Terms--Bulk technologies, neutron and proton effects, soft error rate (SER), single-event upset (SEU).

This paper investigates the sensitivity of SOI and Bulk SRAMs to neutron irradiations with energies from 14 to 500 MeV. The technology sensitivity is analyzed with both experiments and Monte Carlo simulations. In particular, simulations include the nuclear interactions of neutrons with both silicon and oxygen nuclei In-St and n-O), in order to investigate the influence of isolation upper layers on the device sensitivity. The device cross-sections are analyzed for mono-energetic neutron irradiations and discussed in terms of nuclear interaction type (n-St and n-O) and distribution of the secondary ion recoils. We also investigate the dimensions of the interaction volume around the sensitive cell as a function of the device architecture. Index Terms--Bulk technologies, SOI technologies, neutron effects, soft error rate (SER), single-event upset (SEU), Monte Carlo methods.

This paper investigates the sensitivity of bulk technologies in the terrestrial neutron environment as a function of technology scaling. Their sensitivity is analyzed with both experiments and Monte Carlo simulations. The soft error rate (SER) of future technology generations is extrapolated, analyzed and discussed on the basis of different parameters such as the interaction volume, the secondary ion species and the incident neutron energy ranges. Index Terms--Bulk technologies, Monte Carlo methods, neutron effects, soft error rate, single-event upset, SRAM chips.

Results of WNR continuous spectrum irradiations are compared to mono-energetic proton and neutron data according to the JEDEC-JESD89 test procedure. A good correlation between these two methods is found particularly when 500 MeV proton cross-section is used instead of the one at 150 MeV. The increased contribution of the low energy part of the spectrum for modern devices is also discussed. Finally, the influence of front side and back side irradiations is studied at different energies and for several devices from 0.8 [micro]m to 0.18 [micro]m technologies. Index Terms--Bulk technologies, neuron effects, proton effects, soft error rate (SER), single-event upset (SEU).

In this work, we explore the worst case bias response of fully depleted transistors. Floating body and external body ties transistors fabricated on different SOI substrates are characterized using X-rays. The influence of gate length is presented. The coupling effect between front and back gate as well as latch triggered by floating body effect are evaluated as a function of dose level. Index Terms--Buried oxide, charge trapping, fully depleted SOI, latch-up, MOSFET, silicon-on-insulator, total dose irradiation, worst case bias, X-ray effects.

NMOS transistors were irradiated using X-ray, Co-60 gamma, electron, and proton radiation sources. The charge yield was estimated for protons of different energies and electrons, and compared with values obtained for X-ray and Co-60 irradiations. Index Terms--Charge yield, initial recombination, ionizing radiation, metal oxide semiconductor, MOS, total dose, transistors.

This paper analyzes the collected charge in heavy ion irradiated MOS structures. The charge generated in the substrate induces a displacement effect which strongly depends on the capacitor structure. Networks of capacitors are particularly sensitive to charge sharing effects. This has important implications for the reliability of SOI and DRAMs which use isolation oxides as a key elementary structure. The buried oxide of presentday and future SOI technologies is thick enough to avoid a significant collection from displacement effects. On the other hand, the retention capacitors of trench DRAMs are particularly sensitive to charge release in the substrate. Charge collection on retention capacitors participate to the MBU sensitivity of DRAM. Index Terms--Capacitors, charge collection, charge sharing, device simulation, diodes, DRAMs, heavy ion irradiation, isolation oxides, MBU sensitivity, MOS structures, SOI technology, SRAMs, transient currents, trench capacitors.

The sensitivity of SOI technologies to transient irradiations (both dose rate and heavy ions) is analyzed as a function of the technology architecture with experiments and simulations. Two main parameters are considered. First, the thickness of the silicon film, which determines the fully or partially depleted state of SOI devices. This parameter strongly influences the parasitic bipolar, which amplifies the radiation-generated charge. In particular, fully depleted devices show a low bipolar gain due to a high-impact ionization. Secondly, the doping profile in the drain region, which varies with process optimization. The trend is to use shallow junctions to reduce short-channel effects in partially depleted devices. Shallow-drain junctions in partially depleted devices contribute to increases in drain-region sensitivity. As a result, fully depleted architectures are more adapted to reduce the radiation sensitivity of future SOI technologies, because it both reduces the bipolar amplification and the sensitivity of the drain region. Index Terms--Critical charge, cross section, current gain, device simulation, doping profile, dose rate, fully depleted, heavy ion, impact ionization, lightly doped drain, linear energy transfer, MOS transistor, parasitic bipolar transistor, partially depleted, radiation, shallow junction, SOI, SRAM, transient response.

The parasitic bipolar transistor of NMOS/SOI transistors is a key element to determine the single-event upset (SEU) sensitivity. Parasitic bipolar transistor response has been investigated through transient current measurements induced by high energy heavy ions and three-dimensional (3-D) simulations. Experimental results reported allow to estimate the parasitic current gain as a function of the heavy ion location in the MOS transistor. Index Terms--Heavy ion, parasitic bipolar transistor, SOI transistor, transient current measurement.

NMOS transistors were irradiated using X-ray, Co-60 gamma, electron, and proton radiation sources. The charge yield was estimated for protons of different energies and electrons and compared to values obtained for X-ray and Co-60 irradiations. Index Terms--Charge yield, initial recombination, ionizing radiation, metal oxide semiconductor, MOS, total dose, transistors.

The total dose tolerance of parasitic LOCOS field transistors is analyzed using two-dimensional (2-D) self-consistent simulations. The influence of process parameters such as the substrate doping level is examined through both experimental and simulation results to improve the understanding of ionizing effects on isolation. Index Terms--LOCOS, MOSFET, numerical simulations, radiation effects, radiation hardening, total dose effects.

DMILL technology integrates mixed analog-digital very rad-hard (>10 Mrad and > [10.sup.14] neutron/[cm.sup.2]) vertical bipolar, 0.S[[micro]meter] CMOS and 1.2 [[micro]meter] PJFET transistors on SOI substrate. In this paper, after a presentation of the DMILL program goal, we discuss in more detail the main technological choices, the main milestones from the R&D to the industrial implementation, and the main results obtained after stabilization of the final process-flow in the MHS foundry.

A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given 'critical' dose. Above this dose, we still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic conduction is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies.

Radiation-induced trapped charge densities in 45-nm radiation-hardened oxides are estimated via capacitance-voltage (C-V) and thermally stimulated current (TSC) techniques as functions of irradiation and/or isochronal anneal temperature. Reductions in trapped-hole charge were greater for -10 V and 0 V isochronal anneals than for 10 V anneals. This is attributed to enhanced electron-hole dipole pairing during positive-bias anneal. Between 22 [degrees] C and 125 [degrees] C, the trapped electron charge increases for 10 V isochronal anneals, and is approximately constant for 0 V and -10 V anneals. Interface-trap charge decreases for 0 V isochronal annealing above 80 [degrees] C, and [+ or -] 10 V annealing above 100 [degrees] C. Elevated temperature irradiation at 10 V shows similar trends to 10 V isochronal anneals. Trapped-hole energy scales derived from C-V measurements for positive or zero bias isochronal anneals are found to be inaccurate, due to the different temperature dependencies of trapped-hole annealing and trapped-electron buildup. Refined estimates of trapped-hole attempt-to-escape frequency are obtained via TSC. Isochronal annealing and elevated temperature irradiation techniques generally cannot be used for hardness assurance testing unless the results are 'calibrated' to the low-rate irradiation or long-term annealing response for a given technology.

Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. We present, here, a new method to measure and analyse this effect together with a simple model. We also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. We show that it explains some of the upsets observed in a SRAM embedded in an ASIC.

This work concerns the development of a radiation hardness assurance methodology specially devoted to CMOS, JFET and bipolar transistors used in high total dose level environments. On the basis of recent studies, high temperature, high dose rate irradiations were performed. We propose a test procedure which combines high temperature irradiations and isochronal anneals for the qualification.

We have developed a prototype test structure (named THERMOS) demonstrating the feasibility and the interest of the on-chip heating in a Silicon-On-Insulator technology. This circuit has been specially designed for the study of postirradiation effects in a radiation-hardened CMOS technology. Preliminary results are presented here for the on-chip annealing of irradiated n-channel transistors.

This work concerns the development of a methodology specially devoted to lateral parasitic transistors that limit the total dose hardness of CMOS technologies. This methodology is based on i) the irradiation of standard NMOS transistors followed by ii) isochronal annealing measurements to determine energetic spectra of the field oxide trapped charge. Post irradiation effects have been evaluated through additional isothermal annealing experiments at 75 [degrees] C which are consistent with isochronal results. We propose a test procedure which allows to determine physical parameters helpful to improve comparison and qualification of CMOS commercial technologies.

A method combining charge pumping and current-voltage measurements is presented for determining the surface potential versus gate voltage relationship in irradiated MOS transistors. This technique uses parameter optimization and simple numerical equations. It can be applied even for a high interface state density and for a non-uniform distribution in the silicon bandgap. This makes the method attractive for all studies concerning interface trap characterization or accurate modeling of MOS transistors in subthreshold regime. In this study, this new approach is applied to n-channel transistors irradiated up to 10 Mrad (Si[O.sub.2]).

We have performed current-voltage and charge pumping measurements on LOCOS parasitic transistors submitted to x-ray irradiation. The electrical behavior and the charge pumping response of these non-planar structures have been analyzed by two-dimensional computer simulations. We report how this experimental approach allows us to obtain quantitative information about oxide charge and interface trap densities in different parts of the complete structure. Our results show a maximum of oxide charge trapping and interface trap buildup in the bird's beak regions after irradiation. The generation of radiation-induced interface and border traps along the LOCOS Si[O.sub.2]/Si interface is discussed, in terms of trap density and frequency response.

In this work, the evolution of the oxide trapped charge has been modeled, to predict post-irradiation behavior for arbitrary anneal conditions (i.e. arbitrary temperature-time profiles). Using experimental data obtained from a single isochronal anneal, the method consists of calculating the evolution of the energy distribution of the oxide trapped charge, in the framework of a thermally activated charge detrapping model. This methodology is illustrated in this paper by the prediction of experimental isothermal data from isochronal measurements. The implications of these results to hardness assurance test methods are discussed.

Enhanced total dose damage of Junction Field-effect Transistors (JFETs) due to low dose rate and/or elavated temperature has been investigated for elementary p-channel structures fabricated on bulk and SOI substrates as well as for related linear integrated circuits. All these devices were fabricated with conventional junction isolation (field oxide). Large increases in damage have been revealed by performing high temperature and/or low dose rate irradiations. These results are consistent with previous studies concerning bipolar field oxides under low-field conditions. They suggest that the transport of radiation-induced holes through the oxide is the underlying mechanism. Such an enhanced degradation must be taken into account for low dose rate effects on linear integrated circuits.

The trapped charge density in the LOCOS bird's beak resulting from irradiating a conventional NMOSFET has been analysed using a 2D finite element simulation. This paper shows a maximum of trapped charge density in the bird's beak region. The resulting voltage shift of the lateral parasitic transistor in the bird's beak region induces a high leakage current, and prevents any normal circuit operation. The silicon doping level, the supply voltage and the bird's beak shape are key parameters for device hardening of rad-tolerant technologies.

Different electrical characterization techniques (subthreshold current-voltage measurements, standard, 3-level and multi-frequency charge pumping) combined with isochronal anneals have been used to investigate the generation and the evolution of interface traps in radiation-hardened MOS transistors following exposure to 10 keV X-rays. The evolution of the interface state density ([D.sub.it]) during the anneal is found to be field-dependent and consistent with models involving a drift of positive species towards the Si-Si[O.sub.2] interface. The energy-resolved distributions of [D.sub.it] in the silicon bandgap show the emergence of two broad structures located at [approximately] [E.sub.v] + 0.35 eV and [approximately] [E.sub.v] + 0.75 eV immediately after irradiation and during the first steps of the isochronal anneal (up to [approximately] 175 [degrees] C). At higher anneal temperatures, it is shown that the recovery of [D.sub.it] is not uniform in the two halves of the silicon bandgap. In particular, the separation of the [D.sub.it] distribution related to the lower part of the bandgap in two distinct peaks (at [E.sub.v] + 0.30 eV and [E.sub.v] + 0.45 eV) agrees well with the energy distributions of [P.sub.b0] and [P.sub.b1] centers. These results are consistent with Electron Spin Resonance (ESR) studies which have shown that [P.sub.b] centers play a dominating role in the interface trap build-up and recovery mechanisms. Since ESR measurements are only accurate to [approximately] [+ or -]30% in absolute number, [P.sub.b] centers do not probably account for all the electrically active interface trap defects, as also suggested by the evident asymmetry of the [D.sub.it] distributions in the bandgap. Finally, we investigate the post-irradiation response of border traps by reducing the charge pumping frequency to low values. The implication of these results on the nature of border traps is discussed.

High Energy Physics experiments under preparation at CERN (Geneva, Switzerland) with the future LHC (Large Hadron collider) require a fast, low noise, very rad-hard, mixed analog-digital microelectronics VLSI technology. Readout electronics designed using such a technology for the central parts of the LHC particle detectors must withstand more than 10 Mrad (Si[O.sub.2]) and [10.sup.14] neutrons/[cm.sup.2] over 10 years of operation. We present here recent results obtained with a new rad-hard analog-digital technology called [DMILL.sup.1] [1-8], which monolithically integrates NPN bipolar, CMOS and P-JFET transistors, and which has been specifically developed to fulfill the severe constraints of LHC detector readout circuits.

We describe transient effects induced by high energy protons in shift registers processed in a CMOS/thick SOI technology. Devices are tested in dynamic mode. The dependence of cross section on frequency, signal rise time, angle of incidence and proton energy is studied and interpreted.

We have studied the sensitivity of a 256 kbit CMOS/epi SRAM to transient phenomena (protons and ions SEU, dose rate). Local and global failure mechanisms are observed and discussed. For single particles, or at low dose rate, cell upsets are uncorrelated. When the dose rate is increased, correlated failures are due to both cell photocurrent summation (rail span collapse) and supply voltage drop in pheripheral circuits. The transition between uncorrelated to correlated failures is interpreted, on the basis of device structure and pattern influence.

X-ray induced electron and hole trapping properties have been investigated in SIMOX buried oxides of different processes, including standard and supplemental implantation oxides, as well as new thin and ultra-thin oxides. The effect of the substrate bias applied during irradiation is studied, and then used to extract both hole and electron trapping parameters. The results demonstate that varying the oxygen implantation conditions has very little effect on the radiation induced behavior of the material. They show that the charge trapping properties of the buried oxide are related to the ultra high temperature anneal performed on the confined oxide layer, and confirm that the post implantation anneal is the most critical part of the SIMOX process.

We present experimental results from a fast charge amplifier and a wideband analog buffer processed in the DMILL BiCMOS-JFET radhard SOI technology and irradiated up to 4.5 X [10.sup.14] protons/[cm.sup.2]. In parallel, we have irradiated elementary transistors. These components were biased and electrical measurements were done 30 min after beam stop. By evaluating variations of main SPICE parameters, i. e., threshold voltage shift for CMOS and current gain variation for bipolar transistors, we have simulated the wideband analog buffer at different doses. These SPICE simulations are in good agreement with measured circuit degradations. The behavior of the charge amplifier is consistent with extraction of transconductance and pinch-off voltage shift of the PJFET.

We present here recent results obtained on a rad-hard mixed analog-digital technology currently under development, which integrates monolithically complementary MOS transistors (CMOS), complementary JFETs (CJFETs) and complementary bipolar transistors (C-bipolars). This technology is expected to fulfill the hard constraints of LHC detector electronics.

Charge trapping effects in SIMOX buried oxides have been investigated at total doses up to 100 megarad(SiO2) as a function of substrate bias. Hole and electron trapping are controlled by the oxide internal electric field.

CMOS silicon on insulator technology has shown its ability to process hardened components which remain functional after irradiation with a total dose of several tens of Megarads. New tests on elementary transistors and 29101 microprocessor have been made at doses up to 100 Mrad(Si[O.sub.2]) and above. Results of irradiation at these total doses are presented for different biases, together with the post-irradiation behaviour of the components. All the observations show that new parameters must be taken into account for hardness insurance at a high level of total dose.

The isochronal anneal technique used to predict isothermal anneal behavior of MOS devices is analyzed as a function of experimental parameters (bias during irradiation and anneal). This methodology is applied to different oxide types (hardened and unhardened) with different thickness. Net oxide trapped charge is estimated through I-V or C-V measurements, and electron and hole contributions are determined using the TSC technique. The effects of detrapping of trapped holes and compensating electrons are discussed. The prediction of long term post irradiation response can be accurately done when anneals are performed under positive bias. This prediction is more complex for other bias conditions. The difficulty is related to competitive effects of trapped hole annealing and buildup of compensating electrons as a function of temperature. To enable a precise modeling of long term annealing, a complete model must include, among other things, compensation of holes through tunneling, and/or thermally injected electrons.

Radiation-induced hole and electron transport and trapping are fundamental to MOS total-dose models. Here we separate the effects of electron-hole annihilation and electron trapping on the neutralization of radiation-induced charge during switched-bias irradiation for hard and soft oxides, via combined thermally stimulated current (TSC) and capacitance-voltage measurements. We also show that present total-dose models cannot account for the thermal stability of trapped electrons near the Si/Si[O.sub.2] interface, or the inability of electrons in deep or shallow traps to contribute to TSC at positive bias following (1) room-temperature, (2) elevated-temperature, or (3) switched bias irradiation. These results require modifications to modeling parameters and boundary conditions for hole and electron transport in Si[O.sub.2]. Possible types of deep and shallow electron traps in the near-interfacial Si[O.sub.2] are discussed.