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This article investigates the single-event effects on 16-nm bulk field-effect transistors (FinFETS) in terms of single-bit upsets and multiple-cell upsets under heavy ion irradiation. These upsets are analyzed and classified according to voltage, linear energy transfer of ions, data patterns, and fail bit patterns. The analysis suggested a characteristic charge collection mechanism attributable to the FinFET structure. Estimation of a unique sensitive area shape based on cross sections is also discussed. [ABSTRACT FROM AUTHOR]

The impact of back-gate bias on the total ionizing dose (TID) response of silicon-on-insulator (SOI) nanowire field-effect transistors (NWFETs) is investigated. The voltage shift induced by TID is studied using different NWFET geometries and as function of the bias applied to the back-gate made of the silicon substrate. Modifications induced on static electrical characteristics, that is, drain current versus gate-to-source voltage ID(VGS) characteristics, are investigated. Experimental results highlight that the bias applied to the back-gate during I−V measurements strongly impacts the NWFET TID response. At 0 V applied to the back-gate, a usual TID behavior is observed. I−V curves are shifted to negative VGS values, which is consistent with the literature. In contrast, two competing mechanisms are shown when negative biases are applied to the back-gate. ID(VGS) curves are first shifted to positive VGS values for low TID before showing a more usual negative TID-induced voltage shifts. This two-step behavior may be attributed to several phenomena. They include either a modification of the net trapped charge sign for several back-gate biases and/or a motion of carriers trapped into the Buried OXide (BOX). The major goal of this article is to identify the mechanism at stake which drives this combined TID/electrostatic behavior. [ABSTRACT FROM AUTHOR]

We evaluate the total-ionizing-dose (TID) responses of InGaAs nMOS fin field-effect transistors (FinFETs) with a modified gate-stack irradiated with 10-keV X-rays under different gate biases. This modified InGaAs nMOS FinFET process shows decreased subthreshold leakage current and increased hysteresis in as-processed devices, and reduced hole trapping in irradiated devices, than first-generation development-stage devices. The reduction in subthreshold leakage current is attributed to changing the buffer layer from GaAs to In0.3Ga0.7As, thereby enhancing the material quality. Both the increased hysteresis in as-processed devices and reduced hole trapping in irradiated devices are attributed primarily to thinning the Al2O3 layer that separates the HfO2 from the InGaAs layers. This facilitates charge exchange with defects at the HfO2/Al2O3 interface and reduces the percentage of radiation-induced holes that are generated in Al2O3 and trapped in HfO2. The removal of a tungsten layer above the TiN gate reduces the interface dose enhancement. [ABSTRACT FROM AUTHOR]

In this article, we explore different device and standard cell architectures for scaling the Germanium fin field-effect transistor (FinFET) and nanosheet (NS) at the sub-5-nm node. It is demonstrated that the Germanium device provides approximately 70% improvement in drive current and $3.4\times $ less device resistance. The main concern for Germanium devices remains the high leakage current due to the gate-induced drain leakage, which limits their usage to high-speed applications. Overall, Germanium devices require fewer boosters than silicon to scale beyond the 5-nm node. Contact resistivity is found to be a critical knob for Germanium and it can be relaxed to 3e $- 9\,\,\Omega $ -cm2 to meet the power and performance targets for the sub-5-nm node. Moving to the NS helps in relaxing this constraint further. [ABSTRACT FROM AUTHOR]

The total ionizing dose (TID) response of pMOS nanowire field-effect transistors (NWFETs) is investigated using X-ray irradiations. The TID-induced voltage shift is studied using two NWFET widths and four bias configurations. Both the impact of the geometry and the influence of the bias configuration during irradiation on the radiation-induced trapped charges into the buried oxide are thus addressed. The impact of gate length downsizing on the NWFET’s electrical characteristics in several bias configurations is studied and compared to one of the nMOS NWFETs to state on the mechanisms which leads to their TID response. [ABSTRACT FROM AUTHOR]

Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high ION/IOFF ratio (\sim5\times 10^5, at VD=0.1~V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (VTH) shift can be maintained at the level of \sim110~mV/V and \sim0.1~V, respectively, for Ge n-channel FinFET with Lchannel=120~\rm nm and WFin=40~\rm nm. Multifin Ge FinFET with Lchannel=170~\rm nm and WFin=50~\rm nm is also illustrated. Both N- and P-FinFETs possess high ION/IOFF ratio over 10^4. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing. [ABSTRACT FROM AUTHOR]

Abstract: Inherently smaller cross-sectional area of heavily doped source/drain regions (HDDs) in multiple gate transistors is known to give rise to a higher contact resistance between Si and HDD silicide as compared to a planar transistor with similar width of the Si channel. In order to characterize the contact resistance, multiple gate FETs have been fabricated with fin widths and gate lengths down to 18 and 45nm, respectively. Experiments performed by varying layout and technology parameters show that Nickel silicide forms wrapped contacts around HDDs. Further, the silicidation process is shown to be fully siliciding HDDs in devices with narrow fins, where a selective epitaxial growth of Si has been performed in HDDs. [Copyright &y& Elsevier]

Abstract: High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate FETs with narrow fins. Reduction of specific contact resistance by selective epitaxial growth of Si in heavily doped S/D regions of a multiple gate FET helps with achieving low S/D resistance. This paper addresses integration of low temperature selective epitaxial growth process into multiple gate FET processing. Our experimental results show more than 30% reduction in the parasitic S/D resistance for 16-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate NFETs with less than 20-nm wide fins. A follow up of this work with HfO2-TiN gate stack shows more than 20% improvement in the drive current at a constant I OFF for 40-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate FETs. [Copyright &y& Elsevier]

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic s/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node. [ABSTRACT FROM AUTHOR]

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities κ. It is observed that there is a decrease in the parasitic outer fringe capacitance Cof in addition to an increase in the internal fringe capacitance Cif with high-κ dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-κ integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum κ for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering. [ABSTRACT FROM AUTHOR]