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Many shortcomings of chaos-based applications stem from the weak dynamic properties of the chaotic maps they use. To alleviate this problem, inspired by the buffeting effect in aeroelasticity, this article proposes the buffeting chaotification model (BCM). Using the especially designed buffeting and modulo operators, the BCM can generate numerous new chaotic maps with strong dynamic properties from existing one-dimensional chaotic maps. The effectiveness of the BCM is mathematically proven according to the Lyapunov exponent, and further numerical experiments confirm the superiority of the chaotic maps generated by the BCM in terms of the dynamic properties. The field-programmable gate array implementation also shows that the BCM owns simplicity in hardware devices. To investigate the practical application, a scheme for constructing the pseudorandom number generator is designed. Performance analyses indicate that our generators have a strong ability to produce high-quality pseudorandom sequences rapidly. [ABSTRACT FROM AUTHOR]

Neural networks have been widely and deeply studied in the field of computational neurodynamics. However, coupled neural networks and their brain-like chaotic dynamics have not been noticed yet. In this article, we focus on the coupled neural network-based brain-like initial boosting coexisting hyperchaos and its application in biomedical image encryption. We first construct a memristive-coupled neural network (MCNN) model based on two subneural networks and one multistable memristor synapse. Then we investigate its coupling strength-related dynamical behaviors, initial states-related dynamical behaviors, and initial-boosted coexisting hyperchaos using bifurcation diagrams, phase portraits, Lyapunov exponents, and attraction basins. The numerical results demonstrate that the proposed MCNN not only can generate hyperchaotic attractors with high complexity but also can boost the attractor positions by switching their initial states. This makes the MCNN more suitable for many chaos-based engineering applications. Moreover, we design a biomedical image encryption scheme to explore the application of the MCNN. Performance evaluations show that the designed cryptosystem has several advantages in the keyspace, information entropy, and key sensitivity. Finally, we develop a field-programmable gate array test platform to verify the practicability of the presented MCNN and the designed medical image cryptosystem. [ABSTRACT FROM AUTHOR]

One of the main open challenges in the field of learning-based control is the design of computing architectures able to process data in an efficient way. This is of particular importance when time constraints must be met, as, for instance, in real-time decision-making systems operating at high frequencies or when a vast amount of data must be processed. In this respect, field-programmable gate array (FPGA)-based parallel processing architectures have been hailed as a potential solution to this problem. In this article, a low-level design methodology for the implementation on FPGA platforms of Lipschitz interpolation (LI) algorithms is presented. The proposed design procedure exploits the potential parallelism of the LI algorithm and allows the user to optimize the area and energy resources of the resulting implementation. Besides, the proposed design allows to know in advance a tight bound of the error committed by the FPGA due to the representation format. Therefore, the resulting implementation is a highly parallelized and a fast architecture with an optimal use of the resources and consumption and with a fixed numerical error bound. These facts flawlessly suit the desirable specifications of learning-based control devices. As an illustrative case study, the proposed algorithm and architecture have been used to learn a nonlinear model predictive control law applied to self-balance a two-wheel robot. The results show how computational times are several orders of magnitude reduced by employing the proposed parallel architecture, rather than sequentially running the algorithm on an embedded ARM-CPU-based platform. [ABSTRACT FROM AUTHOR]

High-performance Elliptic Curve Cryptography (ECC) implementation in encryption authentication severs has become a challenge due to the explosive growth of e-commerce’s demand for speed and security. Point multiplication (PM) is the most common and complex operation in ECC which directly determines the performance of the whole system. This article proposes a 6CC-6CC (clock cycle) dual-field PM architecture and a 6CC-4CC dual-field PM architecture based on maximizing utilization of Karatsuba multipliers and re-ordering schedule strategy in PM. The Montgomery Ladder algorithm used in PM is modified to a 4CC algorithm for better resource utilization and parallel computation. To solve the frequency drop problem while working on large finite field, the PM architectures for high and low field are carefully studied to have universal critical path length and balanced performance. Both of the architectures are implemented over GF(2571) and GF(2283) on Xilinx Virtex-5 and Virtex-7 FPGAs (Field-Programmable Gate Array) for comparison. The 6CC-6CC architecture is shown to have the best performance on GF(2571), which achieves one PM operation in $17.44~\mu s$ using 81549 LUTs (Look-Up-Table) with the frequency of 197.2 MHz on Virtex-5, and $12.55~\mu s$ using 80970 LUTs with the frequency of 274.1 MHz on Virtex-7. The 6CC-4CC architecture performs better on GF(2283) with the shortest computation time. It takes only $3.21~\mu s$ to finish one PM operation on Virtex-5 and $2.22~\mu s$ on Virtex-7, which are faster than all the previous designs. The implementation results prove that the proposed architectures have state-of-the-art performance as well as higher versatility for ECC designs.

Polynomial functions have been the main barrier restricting the circuit realization and engineering application of multiwing chaotic systems (MWCSs). To eliminate this bottleneck, we construct a simple MWCS without polynomial functions by introducing a sinusoidal function in a Sprott C system. Theoretical analysis and numerical simulations show that the MWCS can not only generate multibutterfly attractors with an arbitrary number of butterflies, but also adjust the number of the butterflies by multiple ways including self-oscillating time, control parameters, and initial states. To further explore the advantage of the proposed MWCS, we realize its analog circuit using commercially available electronic elements. The results demonstrate that in comparison to traditional MWCSs, our circuit implementation greatly reduces the consumption of electronic components. This makes the MWCS more suitable for many chaos-based engineering applications. Furthermore, we propose an application of the MWCS to chaotic image encryption. Histogram, correlation, information entropy, and key sensitivity show that the simple image encryption scheme has a high security and reliable encryption performance. Finally, we develop a field-programmable gate array test platform to implement the MWCS-based image cryptosystem. Both theoretical analysis and experimental results verify the feasibility and availability of the proposed MWCS. [ABSTRACT FROM AUTHOR]

A digital interfacing circuit (DIC) based on sliding discrete Fourier transform (SDFT) bins has been proposed for lossy capacitive sensors. The proposed interfacing circuit consisting of an analog sensing circuit and an analog-to-digital converter (ADC)-field-programmable gate array (FPGA)-based DIC. The sliding DFT bin-1 is employed as a quadrature signal generator to obtain in-phase and quadrature signals of the input supply voltage provided to the analog sensing circuit. The output sinusoidal signal of analog sensing circuit is correlated with the in-phase and quadrature signals separately and then averaged with SDFT bin-0 for computing sensing capacitance and resistance values. The proposed method is implemented in FPGA and tested for capacitance measurement range of 11 pF–5.27 nF with the maximum relative percentage error of 1.36%. The nonlinearity error is < 0.37% FS and FSS. Moreover, the suitability of the proposed interface for humidity measurement has been explored and validated experimentally with saturated salt solutions. Furthermore, the interdigitated capacitance is fabricated and tested with the proposed digital interface for the capacitance range of 30–122 pF, which finds an application in capacitive touchpad. [ABSTRACT FROM AUTHOR]

Cryptography systems have become inseparable parts of almost every communication device. Among cryptography algorithms, public-key cryptography, and in particular elliptic curve cryptography (ECC), has become the most dominant protocol at this time. In ECC systems, polynomial multiplication is considered to be the most slow and area consuming operation. This article proposes a novel hardware architecture for efficient field-programmable gate array (FPGA) implementation of Finite-field multipliers for ECC. Proposed hardware was implemented on different FPGA devices for various operand sizes, and performance parameters were determined. Comparing to state-of-the-art works, the proposed method resulted in a lower combinational delay and area–delay product indicating the efficiency of design. [ABSTRACT FROM AUTHOR]

This article proposes an improved orthogonal matching pursuit (OMP) algorithm and its implementation with Xilinx Vivado high-level synthesis (HLS). We use the Gram–Schmidt orthogonalization to improve the update process of signal residuals so that the signal recovery only needs to perform the least-squares solution once, which greatly reduces the number of matrix operations in a hardware implementation. Simulation results show that our OMP algorithm has the same signal reconstruction accuracy as the original OMP algorithm. Our approach provides a fast and reconfigurable implementation for different signal sizes, different measurement matrix sizes, and different sparsity levels. The proposed design can recover a 128-length signal with measurement number $M=32$ and sparsity $K=5$ and $K=8$ in 13.2 and $21~\mu \text{s}$ , which is at least a 21.9% and 22.2% improvement compared with the existing HLS-based works; a 256-length signal with $M=64$ and $K=8$ in $20.6~\mu \text{s}$ , which is a 24% improvement compared with the existing work; and a 1024-length signal with measurement number $M=256$ and sparsity $K=12$ and $K=36$ in 150.3 and $423~\mu \text{s}$ , respectively, which are close to the results of traditional hardware description language (HDL) implementations. Our results show that our improved OMP algorithm not only offers a superior reconstruction time compared with other recent HLS-based works but also can compete with existing works that are implemented using the traditional field-programmable gate array (FPGA) design route. [ABSTRACT FROM AUTHOR]

For video applications in a special environment such as medical imaging, space exploration, and underwater exploration, the video captured by an image sensor is often deteriorated because of low lighting conditions. Therefore, it is necessary to enhance the part of the image that is too dark to distinguish details while maintaining the remaining part with the same brightness. The retinex algorithm is widely used to restore naturalness of a video, especially exhibiting outstanding performance in the enhancement of a dark area. However, it demands large computational complexity because of its intricate structure, such as the Gaussian filter and exponentiation operations, and consequently, it is difficult to process in real time. This article presents a low-cost and high-throughput design of the retinex video enhancement algorithm. The hardware (HW) design is implemented using a field-programmable gate array (FPGA), and it supports a throughput of 60 frames/s for a $1920 \times 1080$ image with negligible latency. The proposed FPGA design minimizes HW resources while maintaining the quality and the performance by using a small line buffer instead of a frame buffer, by applying the concept of approximate computing for the complex Gaussian filter, and by designing a new and nontrivial exponentiation operation. The proposed design makes it possible to significantly reduce HW resources (up to 79.22% of total resources) compared to existing systems and is compatible with commercialized devices through the standard HDMI/DVI video ports. [ABSTRACT FROM AUTHOR]

In artificial intelligence (AI), proposing an efficient algorithm with an appropriate hardware implementation has always been a challenge because of the well-accepted fact that AI hardware implementations should ideally be comparable to biological systems in terms of hardware area. Active learning method (ALM) is a fuzzy learning algorithm inspired by human brain computations. Unlike traditional algorithms, which employ complicated computations, ALM tries to model human brain computations using qualitative and behavioral descriptions of the problem. The main computational engine in ALM is the ink drop spread (IDS) operator, but this operator imposes high memory requirements and computational costs, making the ALM algorithm and its hardware implementation unsuitable for some of the applications. This paper proposes an adaptive alternative method for implementing the IDS operator; a method which results in a marked reduction in the algorithm's computational complexity and in the amount of memory required and hardware. To check its validity and performance, the method was used to carry out modeling and pattern classification tasks. This paper used challenging and real-world datasets and compared with well-known algorithms (adaptive neuro-fuzzy inference system and multi-layer perceptron) in software simulation and hardware implementation. Compared to traditional implementations of the ALM algorithm and other learning algorithms, the proposed FPGA implementation offers higher speed, less hardware, and improved performance, thus facilitating real-time application. Our ultimate goal in this paper was to present a hardware implementation with an on-chip training that allows it to adapt to its environment without dependency on the host system (on-chip learning). [ABSTRACT FROM AUTHOR]

Copyright of Journal of Data Acquisition & Processing / Shu Ju Cai Ji Yu Chu Li is the property of Editorial Department of Journal of Nanjing University of Aeronautics & Astronautics and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents the design and embedded implementation of a robust controller for the transformerless multilevel active monophase rectifier. In order to reduce the effects caused by the uncertainty originated by the output load, an algebraic estimator is devised. Then, a linear controller based on the exact static error dynamics passive output feedback (ESEDPOF) is proposed, where the uncertainty estimation is taken into account. Since the controller estimator is based on the continuous-time plant model, its real-time implementation on a digital platform requires a discretization of the controller under sufficiently fast sampling, such that the properties of the closed-loop nonlinear sampled-data system are preserved. For this reason, the medium-scale field-programmable gate array Spartan-6 XC6SLX16 is used for implementing the ESEDPOF controller, the online algebraic estimator, the enhanced phase-locked loop, and the multilevel pulsewidth modulator. The parallel processing provided by these devices and the capability in the design of custom modules allow optimizing the hardware description and obtaining an update time for the control law of 9.683 $\mu$ s. Experimental validation shows an excellent dynamical performance and a near-unity power factor. [ABSTRACT FROM AUTHOR]

When chaotic systems are used in different practical applications, such as nonlinear control and cryptography, their complex chaos dynamics are strongly required. However, many existing chaotic systems have simple complexity, and this brings negative effects to chaos-based applications. To address this issue, this paper introduces a sine chaotification model (SCM) as a general framework to enhance the chaos complexity of existing one-dimensional (1-D) chaotic maps. The SCM uses a sine function as a nonlinear chaotification transform and applies it to the output of a 1-D chaotic map. The resulting enhanced chaotic map of the SCM has better chaos complexity and a much larger chaotic range than the seed map. Theoretical analysis verifies the efficiency of the SCM. To show the performance of the SCM, we apply SCM to three existing chaotic maps and analyze the dynamics properties of the obtained enhanced chaotic maps. Performance evaluations prove that the three enhanced chaotic maps have more complicated dynamics behaviors than their seed chaotic maps. To show the implementation simplicity of the SCM, we implement the three enhanced chaotic maps using the field-programmable gate array. To investigate the SCM in practical application, we design pseudorandom number generators using the enhanced chaotic maps. [ABSTRACT FROM AUTHOR]

Today, the large amount of information exchanged among various devices as well as the growth of the Internet of Things (IoT) demand the development of devices that ensure secure communications, preventing malicious agents from tapping sensitive data. Indeed, information security is one of the key challenges to address within the IoT field. Due to the strong resource constraints in some IoT applications, cryptographic algorithms affording lightweight implementations have been proposed. They constitute the so-called lightweight cryptography. A prominent example is the Trivium stream cipher, one of the finalists of the eSTREAM project. Although cryptographic algorithms are certainly simpler, one of their most critical vulnerability sources in terms of hardware implementations is side channel attacks. In this paper, it is studied the vulnerability of field-programmable gate array (FPGA) implementations of Trivium stream ciphers against fault attacks. The design and implementation of a system that alters the clock signal and checks the outcome is also described. A comparison between real and simulated fault injections is carried out in order to examine their veracity. The vulnerability of different versions of the Trivium cipher and their routing dependences has been tested in two different FPGA families. The results show that all versions of the Trivium cipher are vulnerable to fault attacks, although some versions are more vulnerable than others. [ABSTRACT FROM AUTHOR]

A fundamental challenge in dynamic mode atomic force microscopy (AFM) is the estimation of the cantilever oscillation amplitude from the deflection signal, which might be distorted by noise and/or high-frequency components. When the cantilever is excited at resonance, its deflection is typically obtained via narrow-band demodulation using a lock-in amplifier (LIA). However, the bandwidth of this measurement technique is ultimately bounded by the low-pass filter, which must be employed after demodulation to attenuate the component at twice the carrier frequency. Furthermore, to measure the amplitude of multiple frequency components, such as higher eigenmodes and/or higher harmonics in multifrequency AFM, multiple LIAs must be employed. In this paper, the authors propose the estimation of amplitude and phase using a linear time-varying Kalman filter that is easily extended to multiple frequencies. Experimental results are obtained using square-modulated sine waves and closed-loop AFM scans, verifying the performance of the proposed Kalman filter. [ABSTRACT FROM PUBLISHER]

In this paper, we present a novel architecture based on field-programmable gate arrays (FPGAs) for the reconstruction of compressively sensed signal using the orthogonal matching pursuit (OMP) algorithm. We have analyzed the computational complexities and data dependence between different stages of OMP algorithm to design its architecture that provides higher throughput with less area consumption. Since the solution of least square problem involves a large part of the overall computation time, we have suggested a parallel low-complexity architecture for the solution of the linear system. We have further modeled the proposed design using Simulink and carried out the implementation on FPGA using Xilinx system generator tool. We have presented here a methodology to optimize both area and execution time in Simulink environment. The execution time of the proposed design is reduced by maximizing parallelism by appropriate level of unfolding, while the FPGA resources are reduced by sharing the hardware for matrix–vector multiplication across the data-dependent sections of the algorithm. The hardware implementation on the Virtex6 FPGA provides significantly superior performance in terms of resource utilization measured in the number of occupied slices, and maximum usable frequency compared with the existing implementations. Compared with the existing similar design, the proposed structure involves 328 more DSP48s, but it involves $25\,802$ less slices and 1.85 times less computation time for signal reconstruction with $N = 1024$ , $ K = 256$ , and $m = 36$ , where $N$ is the number of samples, $K$ is the size of the measurement vector, and $m$ is the sparsity. It also provides a higher peak signal-to-noise ratio value of 38.9 dB with a reconstruction time of $0.34~\mu $ s, which is twice faster than the existing design. In addition, we have presented a performance metric to implement the OMP algorithm in resource constrained FPGA for the better quality of signal reconstruction. [ABSTRACT FROM AUTHOR]

This paper presents a robust linear generalized proportional integral (GPI) control scheme for the output reference trajectory tracking task on a multilevel single-phase “buck” inverter. The scheme is shown to be robust with respect to arbitrary time-varying load current demands, acting as perturbation inputs to the inverter, and to significant converter parameter variations. The discrete time version of the control scheme is implemented on a field-programmable gate array hardware. Several laboratory robustness tests are performed on the controlled inverter with excellent results. [ABSTRACT FROM PUBLISHER]

We present a directional-edge-based object tracking system based on a field-programmable gate array (FPGA) that can process 640\,\times\,480 resolution video sequences and provide the location of a predefined object in real time. Inspired by biological principle, directional edge information is used to represent the object features. Multiple candidate regeneration, a statistical method, has been developed to realize the tracking function, and online learning is adopted to enhance the tracking performance. Thanks to the hardware-implementation friendliness of the algorithm, an object tracking system has been very efficiently built on an FPGA, in order to realize a real-time tracking capability. At the working frequency of 60 MHz, the main processing circuit can complete the processing of one frame of an image (640\,\times\,480 pixels) in 0.1 ms in high-speed mode and 0.8 ms in high-accuracy mode. The experimental results demonstrate that this system can deal with various complex situations, including scene illumination changes, object deformation, and partial occlusion. Based on the system built on the FPGA, we discuss the issue of very large-scale integrated chip implementation of the algorithm and self initialization of the system, i.e., the autonomous localization of the tracking object in the initial frame. Some potential solutions to the problems of multiple object tracking and full occlusion are also presented. [ABSTRACT FROM PUBLISHER]

This paper demonstrates the hardware implementation of a recently proposed low-power asynchronous Advanced Encryption Standard substitution box (S-Box) design that is capable of being resistant to side channel attack (SCA). A specified SCA standard evaluation field-programmable gate array (FPGA) board (SASEBO-GII) is used to implement both synchronous and asynchronous S-Box designs. This asynchronous S-Box is based on self-time logic referred to as null convention logic (NCL), which supports a few beneficial properties for resisting SCAs: clock free, dual-rail encoding, and monotonic transitions. These beneficial properties make it difficult for an attacker to decipher secret keys embedded within the cryptographic circuit of the FPGA board. Comparisons on the resistance to SCAs of both the original and proposed S-Box design are presented, using differential power analysis (DPA) and correlation power analysis (CPA) attacks. The power measurement results showed that the NCL S-Box had 22%-26% lower total power consumption than the original and was effective against DPA and CPA attacks. An important factor of successfully implementing DPA or CPA attacks, which is the number of power traces, is also analyzed in this paper. [ABSTRACT FROM AUTHOR]

Researchers have shown that the Electronic Product Code (EPC) Class-1 Generation-2 (C1G2) specification has serious security problems. To overcome these weaknesses, some authors have proposed a specially designed pad generation (PadGen) function to improve security. The PadGen function is used to produce a cover-coding pad to mask the tag's access password before the data are transmitted. In this paper, we study the radio-frequency identification (RFID) tag–reader mutual authentication (TRMA) scheme. Two improved authentication protocols for generating the PadGen function are described. A hardware design of these RFID authentication protocols conforming to the International Standards Organization 18000-6 Type-C protocol, also known as EPC C1G2 RFID protocol, is proposed. Since tags have an extremely limited computing power and storage capacity, the PadGen function based on exclusive-or operation for low-cost hardware implementation is reported in this study. The proposed RFID TRMA protocol was simulated using Modelsim XE II and synthesized using Altera's Quartus II software. The functionality of these strengthening protocols was successfully verified in hardware using an Altera DE2 board that included an Altera Cyclone II field-programmable gate array. [ABSTRACT FROM PUBLISHER]

The current stage of railway transportation systems must deal with increased safety and reliability issues. A key point is improving occupancy track circuit performance and providing them with redundancy, higher noise immunity, and the capability to acquire additional information about the track section involved. This work proposes a novel track circuit based on the encoding of the electrical transmissions with Kasami codes. Track circuit emitters send signals coded with a known sequence that can be identified by the corresponding receivers using correlation techniques; these processes increase immunity to noise and changes in environmental conditions. An appropriate selection of orthogonal sequences for encoding, as well as different carrier frequencies for transmissions, allow simultaneous emissions and receptions without cross interference. [ABSTRACT FROM PUBLISHER]

A hybrid protection scheme for bipolar HVDC line has been implemented with field-programmable gate array (FPGA) and evaluation of its performance in real time is described in this paper. The protection scheme amalgamates a traveling wave protection unit, a boundary protection unit, and a lightning unit. A stationary wavelet transform (SWT) and its wavelet modulus maxima are used to remove noise and represent a useful traveling wave signal. Boundary protection based on SWT is used jointly with traveling wave protection to distinguish internal faults from external faults. The lightning unit is used to distinguish non-fault transients and to identify the faulty pole. Xilinx XtremeDSP Development Kit-4 is employed for the hardware implementation, with coding done using the Xilinx System Generator and AccelDSP. The cost-efficient hardware co-simulation approach is adopted here to evaluate the real-time performance of the protection scheme. [ABSTRACT FROM AUTHOR]

Radio-frequency identification (RFID) is a wireless technology that utilizes radio communication to identify objects with a unique electrical identity. The widespread deployment of RFID technologies may generate new threats to security and user privacy. One of the main drawbacks of RFID technology is the weak authentication systems between a reader and a tag. In general, "weak" authentication systems that either leak the password directly over the network or leak sufficient information while performing authentication allow intruders to deduce or guess the password. In this paper, we study the RFID tag-reader mutual authentication scheme. A hardware implementation of the mutual authentication protocol for the RFID system is proposed. The proposed system was simulated using Modelsim XE II and synthesized using Xilinx synthesis technology. The system has been successfully implemented in hardware using an Altera DE2 board that included an Altera Cyclone II field-programmable gate array (FPGA). Finally, the output waveforms from the FPGA were displayed on the 16702A logic analysis system for real-time verification. [ABSTRACT FROM AUTHOR]

We present an area-efficient method and field-programmable gate array (FPGA) realization for two common operations in robotics, namely, the following: 1) rotating a vector in 2-D and 2) aligning a vector in the plane with a specific axis. It is based on a new coordinate rotation digital computer (CORDIC) algorithm that is designed to work with a small set of elementary angles. Unlike conventional CORDIC, the proposed algorithm does not require a ROM and a full-fledged barrel shifter. The proposed CORDIC algorithm is used to design hardware-efficient solutions for two mobile robotic tasks in an indoor environment without employing division and floating-point calculations. Experiments with a sole low-end FPGA -based robot in static as well as dynamic environments validate the power of the approach. [ABSTRACT FROM AUTHOR]

This paper presents a fast hardware-efficient logic for fault detection and classification in transmission lines, implemented using a field-programmable gate array (FPGA). The general-purpose SPARTAN3E FPGA was employed for developing the prototype, with all the coding done using a hardware description language (HDL) called very high speed integrated circuit (VHDL). The proposed logic employs only one-terminal current samples and is based on wavelet analysis. Depending on the amount of high frequency components in the current signals after processing, the faults are classified into ten types. The Real Time Windows Target Toolbox of MATLAB was used to apply the current signal inputs to the prototype in real time. An adaptive threshold value is chosen, rather than a fixed threshold in the case of faults involving the ground, to make the classification reliable and accurate. The fault classification time is 6 ms, which is about 1/3 of the power frequency cycle (20 ms). A high level of computational efficiency is achieved as compared to the other wavelet-transform-based algorithms, since only the high frequency details at first level are employed in this algorithm. The validity of the proposed logic was exhaustively tested by simulating various types of faults on a system modeled in the Electromagnetic Transients Program/Alternative Transients Program. The proposed logic was found to be highly reliable and accurate, even in the presence of fault resistance. [ABSTRACT FROM AUTHOR]

Explicit finite difference (FD) schemes can realize highly realistic physical models of musical instruments but are computationally complex. A design methodology is presented for the creation of field-programmable gate array (FPGA)-based micro-architectures for FD schemes which can be applied to a range of applications with varying computational requirements, excitation and output patterns and boundary conditions. It has been applied to membrane and plate-based sound producing models, resulting in faster than real-time performance on a Xilinx XC2VP5O device which is 10 to 35 times faster than general purpose and digital signal processors. The models have developed in such a way to allow a wide range of interaction (by a musician) thereby leading to the possibility of creating a highly realistic digital musical instrument. [ABSTRACT FROM AUTHOR]

This paper proposes a novel wavelet-transform-based directional algorithm for busbar protection. The algorithm decomposes the current and voltage signals into their first-level details, which consist of frequencies in 500- to 1000-Hz bandwidth, for generating directional signals. A high level of computational efficiency is achieved compared to the other wavelet-transform-based algorithms proposed, since only the high-frequency details at the first level are employed in this algorithm. The validity of this method was exhaustively tested by simulating various types of faults on a substation modeled in the Alternative Transients Program/Electromagnetic Transients Program. The algorithm correctly discriminated between bus faults, various types of external faults, and transformer energization even in the presence of current-transformer saturation. This paper also provides the design details of the algorithm using field-programmable gate array technology. [ABSTRACT FROM AUTHOR]

The reduced visibility graph (RVG) is an important structure for computation of shortest paths for mobile robots. An efficient bit representation is proposed to construct segments that are part of the RVG. Based on the bit representation, a hardware-efficient scheme is presented whose computational complexity is O(k² log(n/k)), where k is the number of objects and n is the total number of vertices. An architecture that accomplishes the construction of the RVG without division or explicit intersection point calculations is proposed. An efficient field-programmable gate array implementation using block random access memory on an XCV3200E device is presented. [ABSTRACT FROM AUTHOR]

This paper presents a flexible 2 × 2 matrix multiplier architecture. The architecture is based on word-width decomposition for flexible but high-speed operation. The elements in the matrices are successively decomposed so that a set of small multipliers and simple adders are used to generate partial results, which are combined to generate the final results. An energy reduction mechanism is incorporated in the architecture to minimize the power dissipation due to unnecessary switching of logic. Two types of decomposition schemes are discussed, which support 2's complement inputs, and its overall functionality is verified and designed with a field-programmable gate array (FPGA). The architecture can be easily extended to a reconfigurable matrix multiplier. We provide results on performance of the proposed architecture from FPGA post-synthesis results. We summarize design factors influencing the overall execution speed and complexity. [ABSTRACT FROM AUTHOR]

This paper presents a new kind of architecture for artificial digital neurons based on the voting circuit, which may be considered an improved version of those presented in literature. Stochastic pulse modulation has been used, where the values of the neuron's inputs are coded in terms of bit probabilities. The resulting activation function closely resembles the logistic sigmoid, with a transition slope that can be selected at the architectural level with no additional hardware requirements. The proposed neuron architecture has been simulated in software. Simulation results confirm that the neuron features a sigmoid transfer characteristic similar to that of conventional voting circuits. The resource occupation of the neuron, as obtained from implementation on reconfigurable platforms, has been estimated to be significantly lower than previous implementations. The theoretical analysis of the neuron's behavior is also presented. [ABSTRACT FROM AUTHOR]

Recurrent neural networks have interesting properties and can handle dynamic information processing unlike ordinary feedforward neural networks. However, they are generally difficult to use because there is no convenient learning scheme. In this paper, a recursive learning scheme for recurrent neural networks using the simultaneous perturbation method is described. The detailed procedure of the scheme for recurrent neural networks is explained. Unlike ordinary correlation learning, this method is applicable to analog learning and the learning of oscillatory solutions of recurrent neural networks. Moreover, as a typical example of recurrent neural networks, we consider the hardware implementation of Hopfield neural networks using a field programmable gate array (FPGA). The details of the implementation are described. Two examples of a Hopfield neural network system for analog and oscillatory targets are shown. These results show that the learning scheme proposed here is feasible. [ABSTRACT FROM AUTHOR]