High-speed fault classification in power lines: Theory and FPGA-based implementation

This paper presents a fast hardware-efficient logic for fault detection and classification in transmission lines, implemented using a field-programmable gate array (FPGA). The general-purpose SPARTAN3E FPGA was employed for developing the prototype, with all the coding done using a hardware description language (HDL) called very high speed integrated circuit (VHDL). The proposed logic employs only one-terminal current samples and is based on wavelet analysis. Depending on the amount of high frequency components in the current signals after processing, the faults are classified into ten types. The Real Time Windows Target Toolbox of MATLAB was used to apply the current signal inputs to the prototype in real time. An adaptive threshold value is chosen, rather than a fixed threshold in the case of faults involving the ground, to make the classification reliable and accurate. The fault classification time is 6 ms, which is about 1/3 of the power frequency cycle (20 ms). A high level of computational efficiency is achieved as compared to the other wavelet-transform-based algorithms, since only the high frequency details at first level are employed in this algorithm. The validity of the proposed logic was exhaustively tested by simulating various types of faults on a system modeled in the Electromagnetic Transients Program/Alternative Transients Program. The proposed logic was found to be highly reliable and accurate, even in the presence of fault resistance. � 2009 IEEE.