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Synchronously sampling three-phase current in the traction control unit based on the control cycle is necessary to enhance control of permanent magnet synchronous motors. Simultaneously, continuous current sampling at small time intervals is essential for realtime over-current protection. This paper presents a solution based on a field-programmable gate array (FPGA), which incorporates a single set of analog-to-digital converter (ADC) chips to enable both synchronous current sampling essential for controlling permanent magnet synchronous motors and fast timed sampling necessary for real-time over-current protection. This design intelligently generates ADC conversion start signals through acquiring user-configured synchronous sampling periods in real time alongside timed sampling periods, thus enabling synchronous and timed current sampling control for permanent magnet synchronous motors. Finally, experiments were conducted on an actual permanent magnet traction control platform to verify the feasibility and effectiveness of the proposed scheme.

Copyright of Journal of Data Acquisition & Processing / Shu Ju Cai Ji Yu Chu Li is the property of Editorial Department of Journal of Nanjing University of Aeronautics & Astronautics and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Aiming at the position control problem of a 7 degree of freedom (7 DOF) manipulator in the presence of model uncertainty and unknown external disturbances such as friction and gravity, a 7 DOF manipulator driving integrated controller was developed. Firstly, a 7 DOF robotic arm drive control based on advanced risc machines (ARM) + digital signal processor (DSP) + field programmable gate array (FPGA) architecture was designed. The integrated controller scheme was ensured sufficient computing performance. Secondly, a 7 DOF manipulator multi-motor cooperative control method was proposed to improve the accuracy and stability of the manipulator position control system. Then, a nonlinear disturbance observer and the composite control law of the fast-continuous non-singular terminal synovium was used to compensate for external disturbances and system uncertainty, while ensuring the rapid convergence of the system. Finally, the experiments of the position control, speed control, constant torque control and sliding mode position control based on nonlinear disturbance observer were carried out. The effectiveness of the driving integrated control scheme and the composite control strategy was verified. The research results show that the adopted drive-control integrated controller and multi-motor position synergistic control method can ensure that the steady-state error of the position, speed and constant torque control of the joint motor of the 7 DOF manipulator is within 1%. The design based on nonlinear disturbance observer compared with the proportional integral derivative (PID) position control, the performance of overshoot, response speed and steady-state accuracy are improved by 10%～15%. It meets the requirements of high-speed and high-precision servo control of the robotic arm. [ABSTRACT FROM AUTHOR]

Aiming at the problem of non-linearity between desired output and the input of a proportional solenoid valve amplifier without external feedback signal, the function of each parameter in the operation of the amplifier was studied, and a method to implement a linear amplifier by pre-storing matching parameters and executing no tracking during current jump was proposed. Firstly, the problems that need to be solved effectively in realizing linear amplifier were defined. Secondly, based on those problems, through analysis of the existing amplifiers using TRIZ, the solution of inventive principles was obtained. Then, according to the solution, the control value-output current relationship was formed into an inverse matching table, the output current-sampling current relationship was formed into another matching table, and the two matching tables were pre-stored in the amplifier. Finally, the control functions of the amplifier were realized in field programmable gate array (FPGA), and the measurement of matching parameters, test of static performance of the amplifier, and verification of engineering application were carried out for different proportional valves. The research results show that the implementation of the digital linear amplifier is reasonable and effective, with linear error between the input/output less than 1.5%and the current steady-state establishment time less than 0.1 s. The amplifier can be applied in the hydraulic system, reducing complexity of its control system. The control system can exchange parameters with the amplifier on time, which is convenient for remote control. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In the automatic analysis of retinal images, the location of optic disc and macula fovea is a prerequisite for computer aided diagnosis or screening of diabetic retinopathy. In this paper, a novel algorithm for locating the optic disc and macula fovea in retinal images based on YOLOv4-tiny is proposed and transplanted to field programmable gate array (FPGA) platform. Compared with the traditional method, the present work can not only locate the position of the disc and macula in retinal images simultaneously, quickly and precisely, but also be the first attempt to realize 38 layers mediumsized neural network through using high level synthesis (HLS) language and time division multiplexing technology. The COCO data set and 381 retinal images from the recognized Kaggle-Diabetic Retinopathy Detection competition are used in the training experiment. From the experimental results, the mean average precision (mAP) of optic disc and macular fovea localization after transplanting to FPGA platform is 96.11%, and it only takes 150.445 ms to detect an image on the FPGA system, which presents a good clinical application prospect in related fields. [ABSTRACT FROM AUTHOR]

In recent years, traditional computer architectures have gradually been faced with severe bottlenecks of "Memory Wall" and "Power Wall", with the step-down Moore􀆳s law. However, many other new forms of computing paradigms and computer architectures have been proposed, including neuromorphic computing. Given the characteristic of computing in memory, neuromorphic computing plays a vital role in breaking down the limitation caused by both "Memory Wall" and "Power Wall" constraints in Von Neumann architecture. Many neuromorphic applications on neuromorphic processors have already been demonstrated as high efficiency and accuracy. Currently, in the application scenarios of large-scale biological neural networks, it is necessary to improve the scalability of multi-core neuromorphic processors and maintain their high data throughput and low transmission delay. Today, most multi-core neuromorphic processors adopt a network-on-chip (NoC) as the interconnect structure. However, there are still relatively few verification studies on such NoC. Given the importance of NoC in designing a neuromorphic processors, it is quite necessary to set up a complete and robust NoC functional verification platform for neuromorphic processors. The purpose of this paper is to generate the stimulus files required for behavioral and FPGA hardware-level testing based on the randomization method, and to achieve a more comprehensive functional verification through efficient processing of log files. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

A method to implement DMA controller of PCIe bus interface based on Altera FPGA PCIe PHY IP and Synopsys PCIe Core IP was proposed in this paper，and a 4-lane PCIe transmission system was builted. The correctness of reading and writing data was proved through the stimulation in Synopsys VIP environment and transfer verification in Altera Stratix V EX series FPGA platform. The bandwidth of DMA read and DMA write can achieve 1 547 MB/s and 1 607 MB/s respectively. The DMA controller can satisfy the demands of data transfer rates in most practical applications.

Copyright of Piezoelectrics & Acoustooptics is the property of Piezoelectric & Acoustooptic and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Journal of The Iraqi University is the property of Republic of Iraq Ministry of Higher Education & Scientific Research (MOHESR) and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Piezoelectrics & Acoustooptics is the property of Piezoelectric & Acoustooptic and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper an architecture has been proposed for the 2-D Discrete Wavelet Transform (DWT) and the Inverse Discrete Wavelet Transform (IDWT) based on the Convolution method of the Daubechies 5/3-tap Biorthogonal filter bank in the Algorithm transformto image processing, and implementation it on the FPGA (Field Programmable Gate Array) using VHDL, for benefiting from implementation advantages of these Hardware and save run-time. The processing results proved speed and Efficiency of the proposed architecture, where the employed number of slices is less. So it result to Frequency higher and less run-time.The type of the FPGA based in this paper is Xilinx XC3S500E Spartan-3E using Xilinx ISE 9.2i.

In order to remove the interference phenomenon among the measured signals and reduce the waste of FPGA I/ O port resource as the differential flying lines used in the FPGA tested by the logic analyzer, a test interface circuit of -FPGA for logic analyzer is proposed. The design scheme consists of the signal input interface module,differential signal module for the single ended signal and the signal output interface module. The signal input interface module is to complete the signal transmission between FPGA and test interface circuit. The differential signal module is to convert the single ended signal into the differential signal. The signal output interface module is to output the signal converted by the logic analyzer. The FPGA signal is tested as the sampling depths 1 KB, 8 KB and 32 KB,respectively. The experiments confirm that the relative errors of measurement using the test interface circuit are 87.3％,90.2％ and 88.6％, respectively, less than those without using the test interface circuit. [ABSTRACT FROM AUTHOR]

AES, is the well-accepted cryptographic algorithm which could be utilized to ensure security of electronic information since it is proven to be resistive to most of the attacks. In this work, we present the AES-128 encryption and decryption circuit using area optimized iterative architecture. Here the technique used to obtain a lower area delay product is to map the transformations to 8 bit hardware while keeping the datapath to be 128 bit. A control unit is designed to keep track of the transformations. The proposed architecture have been implemented on the most recent Xilinx Spartan FPGA, their area and delay are compared with the previous works and it is proved that proposed technique has lower area coverage and delay. [ABSTRACT FROM AUTHOR]

Copyright of Electric Machines & Control / Dianji Yu Kongzhi Xuebao is the property of Electric Machines & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In order to effectively reduce Turbo decoding complexity in hardware implementation and reduce its resource consumption, an improved Turbo decoding algorithm named improved- Max-Log-MAP is proposed. This new algorithm is a compromise algorithm between Log-MAP algorithm and Max-Log-MAP algorithm and it's more suitable for parallel calculation. This new algorithm replaces the multi-input operation-max (·) with the operation-max which only calculates the maximum value while the algorithm still uses the operation-max (·) in the case of two input variables. The simulation results indicate that improved-Max-Log-MAP algorithm's complexity is approximate to Max-Log-MAP algorithm and while the performance is approximate to Log-MAP algorithm. When Turbo codec using the new algorithm is implemented on FPGA and applied to LEO satellite communication systems, it obtains excellent performance with low complexity and resource consumption, which can help reduce power consumption and size of LEO satellite handheld communication terminal. [ABSTRACT FROM AUTHOR]

An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period, especially considering the influence of the in-out degree of the critical combinational elements. Firstly, the critical elements are selected from all the critical combinational elements to retime. Secondly, for the nodes that cannot be performed with such retiming, register sharing is implemented while the path delay is kept unchanged. The incremental algorithm can be applied with the technology mapping to minimize the critical path delay and obtain fewer registers in the retimed circuit with the near-optimal clock period. Compared with Singh's incremental algorithm, experiments show that the proposed algorithm can reduce the flip-flop count by 11% and look-up table(LUT) count by 5% while improving the minimum clock period by 6%. The runtime is also reduced by 9% of the design flow. [ABSTRACT FROM AUTHOR]

Development of practical algorithms for beamforming in 3G CDMA systems and their software radio implementations are still a challenging task, which will facilitate upgrading of traditional base stations into smart antenna capable 3G base stations. In this paper, we propose a practical space-code correlator (SCC) receiver structure for its software radio implementation a DSP. SCC’s advantage comes from the fact that it doesn’t require any training sequence or learning parameter as in other algorithms (LMS or CM). DSP implementations of the SCC are performed using Texas Instruments C67xx family platforms. In the simulations, reverse link base band signal format of CDMA2000 is used and the effects of different array topologies (uniform linear array-ULA or uniform circular array-UCA) are considered. The implementation results regarding beamforming accuracy, weight vector computation time (execution time), search resolution effect on DOA estimation accuracy, DSP resource utilization, and received SINR are presented. The results show that DSP based SCC beamformer can estimate weight vectors within less than 10 ms with DOA search resolution of 2° especially when C6713 DSP is used. With faster DSPs and larger search resolutions, execution time could be significantly reduced as well. It provides comparable SINR performance with LMS and CM algorithms. [ABSTRACT FROM AUTHOR]

Presents a new full-digital feed-forward auto gain contnol(AGC) algorithm aiming at the problem that the digital jam elimination's outputs have large dynamic range in the anti-jamming navigation receiver. Studies all parameter's of setting methods and points out the field programmable gate array (FPGA) implementation tips. In order to make outputs reach the anticipated ranges, only one-step gain adjustment is needed. Simulations indicate that appropriate gain control factor precision ensures the performance of full-digital feed-forward AGC for various virtual-bit inputs. [ABSTRACT FROM AUTHOR]

An encoder architecture of low density parity check(LDPC) code defined in DVB-S2 standard is proposed. The power dissipation of the computation circuit is reduced obviously through the smart exploitation of the random characteristic of the input data sequence. Furthermore, a design scheme of LDPC encoder with two parallel inputs is presented, which doubles the processing information rate. The multi-rate LDPC encoder with two parallel inputs was implemented on the field programmable gate array (FPGA) XC4VLX25-10SF363, and was tested under the experimental system. The tested results showed that the encoder could work normally with the processing rate up to 328 Mbit/s, which could satisfy the requirements of high speed synchronous digital hierarchy(SDH) transmission application. Additionally, this encoder is flexible to implement encoding of LDPC code with similar parity check matrices via reconfiguration. [ABSTRACT FROM AUTHOR]