一种用于逻辑分析仪的FPGA测试接口电路.

In order to remove the interference phenomenon among the measured signals and reduce the waste of FPGA I/ O port resource as the differential flying lines used in the FPGA tested by the logic analyzer, a test interface circuit of -FPGA for logic analyzer is proposed. The design scheme consists of the signal input interface module,differential signal module for the single ended signal and the signal output interface module. The signal input interface module is to complete the signal transmission between FPGA and test interface circuit. The differential signal module is to convert the single ended signal into the differential signal. The signal output interface module is to output the signal converted by the logic analyzer. The FPGA signal is tested as the sampling depths 1 KB, 8 KB and 32 KB,respectively. The experiments confirm that the relative errors of measurement using the test interface circuit are 87.3％,90.2％ and 88.6％, respectively, less than those without using the test interface circuit. [ABSTRACT FROM AUTHOR]